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pm73488 qse pmc-sierra, inc. long form data sheet pmc-980616 issue 3 5 gbit/s atm switch fabric element released datasheet pm73488 qse 5 gbit/s atm switch fabric element datasheet released issue 3: june 1999
copyright ? 1999 pmc-sierra, inc. all rights reserved pm73488 qse pmc-sierra, inc. pmc-980616 issue 3 5 gbit/s atm switch fabric element released datasheet aal1gator, aal1gator2, evil twin switching, qrt, qse, and saturn are trademarks of pmc-sierra, inc. amcc is a registered trademark of applied microcircuits corporation. i960 is a registered trademark of intel corporation. national semiconductor is a registered trademark of national semiconductor corporation. vitesse is a trademark of vitesse semiconductor corporation. all other brand or product names are trademarks of their respective companies or organizations. u.s. patents 5,557,607, 5,570,348, and 5,583,861
? 1999 pmc-sierra, inc. 105-8555 baxter place burnaby bc canada v5a 4v7 phone: 604.415.6000 fax: 604.415.6200 pmc-sierra, inc. pm73488 qse pmc-980616 issue 3 5 gbit/s atm switch fabric element released datasheet public revision history issue number issue date details of change issue 1 march 1998 creation of document issue 2 october 1998 fixed all known typos/errors ( e.g. wrong pin- out: ram_add(16) and ram_parity swapped ). issue 3 june 1999 production release version
pmc-sierra, inc. pm73488 qse long form data sheet pmc-980616 issue 3 5 gbit/s atm switch fabric element released datasheet table of contents description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 switching algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 multicast support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 diagnostic/robustness features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 i/o features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 physical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 1 how the qse fits into your system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 1.1 qse system overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 1.2 32 x 32 switch application (5 gbps) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 1.3 64 x 64 switch application (10 gbps) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 1.4 5 gbps to 20 gbps application example - seamless growth. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 1.5 5 gbps to 160 gbps application example C lan-to-wan. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2 theory of operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 2.1 phase aligners . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 2.2 data drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 2.3 unicast routing and distribution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 2.4 multicast cell flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 2.4.1 multicast queue engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 2.4.2 multicast dequeue engine. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 2.5 arbiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 2.6 bp_ack drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 2.7 interdevice interconnectability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 2.8 network topologies and the speedup factor (sf) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 2.8.1 network philosophy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 2.8.2 network definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 2.8.3 speedup factor (sf) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 3 external port descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 3.1 switch fabric port and interface description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 3.1.1 se_soc encodings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 3.1.2 data cell format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 3.1.3 bp_ack encodings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 3.2 data acknowledge. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 3.3 microprocessor interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 3.4 multicast sram interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 3.5 clocks and timing signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 3.6 ctrl_in . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 3.7 stat_out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 3.8 fabric switch-over . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
pmc-sierra, inc. pm73488 qse long form data sheet pmc-980616 issue 3 5 gbit/s atm switch fabric element released datasheet 3.9 cell timing/latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 4 qse feature descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 4.1 distribution algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 4.2 cell start offset logic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 4.2.1 relation between external cell_start and local cell_start . . . . . . . . . . . . . . . . . . . . . . 47 4.2.2 relation between local cell_start and data out of the qse . . . . . . . . . . . . . . . . . . . . . . . . . 48 4.3 general description of phase aligners . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 4.4 multicast backpressure control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 4.5 multilevel reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 5 fault specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 5. 1 purpose . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 5. 2 basic data and bp/ack flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 5. 3 fault detection mechanisms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 5. 4 interface behavior. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 5. 5 irt-to-switch fabric interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 5. 6 qse interface, receive data direction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 5. 7 qse interface, transmit data direction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 5. 8 switch fabric-to-ort interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 5. 9 types of failures and their manifestation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 6 signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 6.1 package diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 6.2 signal locations (signal name to ball) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 6.3 signal locations (ball to signal name) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 6.4 pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 6.4.1 processor interface signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 6.4.2 multicast ram interface signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 6.4.3 qse interface signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 6.4.4 boundary scan signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 6.4.5 miscellaneous signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 6.4.6 total pin count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 7 physical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 8 timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 8.1 microprocessor timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 8.2 ram timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 8.3 qse interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 8.4 miscellaneous timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 9 microprocessor ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 9.1 microprocessor ports summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 9.2 note on error detection and reporting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 9.3 microprocessor ports bit definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 9.3.1 revision. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 9.3.2 chip_mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
pmc-sierra, inc. pm73488 qse long form data sheet pmc-980616 issue 3 5 gbit/s atm switch fabric element released datasheet 9.3.3 multicast_group_index_register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 9.3.4 multicast_group_vector_register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 9.3.5 multicast_group_op . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 9.3.6 uc/mc_fairness_register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 9.3.7 extended_chip_mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 9.3.8 multicast_group_index_msb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 9.3.9 input_port_enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 9.3.10 output_port_enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 9.3.11 input_marked_cells_count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 9.3.12 output_marked_cells_count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 9.3.13 parity_error_present . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 9.3.14 parity_error_latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 9.3.15 parity_error_int_mask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 9.3.16 se_input_port_fail_present . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 9.3.17 se_input_port_fail_latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2 9.3.18 bp_ack_fail_present . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 9.3.19 bp_ack_fail_latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 9.3.20 bp_remote_fail_present . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 9.3.21 bp_remote_fail_latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 9.3.22 control_register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 9.3.23 interrupt_status_register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 9.3.24 multicast_aggregate_output_and_input_modes . . . . . . . . . . . . . . . . . . . . . . 105 9.3.25 unicast_aggregate_output_mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 9.3.26 switch_fabric_row . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 9.3.27 switch_fabric_column . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 9.3.28 cell_start_offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 9.3.29 bp_control_register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 9.3.30 ack_payload . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 9.3.31 gang_dead_ack_payload . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 9.3.32 extended_switch_mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 10 10 jtag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 10.1 jtag support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 10.2 tap controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 10.2.1 test-logic-reset: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 10.2.2 run-test-idle: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 10.2.3 capture-dr:. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 10.2.4 shift-dr: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 10.2.5 update-dr: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 10.2.6 capture-ir: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 10.2.7 shift-ir: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 10.2.8 update-ir: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 10.3 boundary scan instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
pmc-sierra, inc. pm73488 qse long form data sheet pmc-980616 issue 3 5 gbit/s atm switch fabric element released datasheet 10.3.1 bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 10.3.2 extest . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 10.3.3 sample . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 10.3.4 idcode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 10.3.5 stctest . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 10.4 boundary scan pin order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
pmc-sierra, inc. pm73488 qse long form data sheet pmc-980616 issue 3 5 gbit/s atm switch fabric element released datasheet list of figures figure 1. qse interface block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 2. qse system overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 3. 32 x 32 switch application (5 gbps) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 4. 64 x 64 switch application (10 gbps) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 5. 5 gbps atm switch using 8 qrts, and 1 qse . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 6. 10 gbps atm switch using 16 qrts, and 2 qses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 7. 20 gbps atm switch using 32 qrts, and 4 qses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 8. 5 gbps to 160 gbps switches modeled using only two cards . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 9. 5 gbps atm switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 10. 10 gbps atm switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 11. 15 gbps atm switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 12. 20 gbps atm switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 13. basic qse flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 14. routing bits rotation for unicast traffic, gang mode of four . . . . . . . . . . . . . . . . . . . . . . . 24 figure 15. example of multicast cell handling in the qse . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 16. ideal distributed network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 17. more realistic distributed network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 18. large distributed network (will not work well with banyan alone) . . . . . . . . . . . . . . . . 30 figure 19. high-level qrt/qse system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 figure 20. (3) x 1 - 5 gbps system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 figure 21. (5) x 4 - 20 gbps system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 figure 22. (1,3) x 1 - 10 gbps system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 figure 23. randomizer (with evil twin switching algorithm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 figure 24. network needs to be run faster than the line rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 figure 25. definition of the speedup factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 figure 26. how to use the sf to select favorable networks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 4 figure 27. se_soc encodings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 figure 28. expanded se_soc encodings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 figure 29. bp_ack encodings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 figure 30. qse cell-level timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 figure 31. qse switch latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 figure 32. basic forward and backward data path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 figure 33. basic data path (se_d_out/in and se_soc_out/in in forward path, bp_ack_out/in in backward path) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 figure 34. 596-ball enhanced plastic bga physical dimensions diagram (top view) . . . . . . . . . . . . . 55 figure 35. 596-ball enhanced plastic bga physical dimensions diagram (bottom view) . . . . . . . . . . . 56 figure 36. qse pinout block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 figure 37. microprocessor timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
pmc-sierra, inc. pm73488 qse long form data sheet pmc-980616 issue 3 5 gbit/s atm switch fabric element released datasheet figure 38. ram interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 figure 39. qse bit-level timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 figure 40. reset timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 figure 41. jtag timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 figure 42. boundary scan architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 figure 43. tap controller finite state machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
pmc-sierra, inc. pm73488 qse long form data sheet pmc-980616 issue 3 5 gbit/s atm switch fabric element released datasheet list of tables table 1. bp_control_register; threshold control bits for each set of 32 buffers . . . . . . . . . . . 25 table 2. speedup factor (1-stage networks) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 3. speedup factor (3-stage networks) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 5. regular cell format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 6. pm73488 mode idle cell format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 7. information bit encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 table 8. data latencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 table 9. failure conditions, irt-to switch fabric interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 table 10. failure conditions, qse receive interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 table 11. failure conditions, qse transmit interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 table 12. failure conditions, switch fabric-to-ort interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3 table 13. faults . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 table 14. signal locations (signal name to ball) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 table 15. signal locations (ball to signal name) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 table 16. processor interface signals (21 signal pins) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 table 17. multicast ram interface signals (39 signal pins) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 table 18. qse interface signals (364 signal pins) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 table 19. boundary scan signals (8 signal pins) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 table 20. miscellaneous signals (8 signal pins) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 table 21. pin allocations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 table 22. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 table 23. recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 table 24. dc operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 table 25. capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 table 26. estimated package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 table 27. microprocessor timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 table 28. ram interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 table 29. ctrl_in, stat_out, test_mode and debug timing . . . . . . . . . . . . . . . . . . . . . . . . . 86 table 30. valid window timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 table 31. microprocessor ports summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 table 32. boundary scan pin order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 table 33. standard abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 table 34. ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
pmc-sierra, inc. pm73488 qse long form data sheet pmc-980616 issue 3 5 gbit/s atm switch fabric element released datasheet 13 wac-488-b product overview description the pm73488 (qse) is an advanced communications device that enables the implementation of high performance switching systems. the qse is a 32 32 cell based switch element, with a total sustainable bandwidth of 5 gb/s. (the peak , or raw, bandwidth is much more than that: about 8 gb/s). the qse is designed to be used with other qses as part of a larger switch fabric. various qse combinations allow fabrics with theoretical peak capacities ranging from 5 gb/s (one qse) to 160 gb/s. the qse is not atm specific; however, should the qse be used for switching atm cells, the qse cell size is large enough to allow efficient direct mapping between qse cells and atm cells. multistage qse fabrics (delta-reverse delta configuration) have rich connectivity with multiple paths between each source/destination pair. a qse fabric performs cut-through unicast switching and uses randomization and evil-twin algorithms to fully utilize these multiple paths and avoid the build up of internal hot spots. randomization, in combi- nation with multiple routing paths allows graceful degradation of qse fabric performance if internal links fail. to detect failed links, the qse maintains and checks liveness patterns on input and output ports in hardware, and automatically routes around ports if they die. qse data ports are 6 bits wide including a 4-bit wide 66 mhz data path, a one-bit wide start-of-cell indication, and a one-bit wide acknowledgment signal. each port contains "phase aligners" to recover the clock for that port, thus removing the need to synchronize all data to a single global clock. when switching unicast traffic in a multistage fabric (one to three stages), the first nibble of the cell will come out of the last qse stage before the last nibble of that cell enters the first stage. the cell thereby traverses the entire fabric in one cell time. if the cell sucessfully makes it to its destination, the ("egress") device accepting the cell from the last stage qse has the opportunity to send a four bit "ack information packet" back to source indicating what it did with this cell; at its simplest, the egress device can send back one pattern to indicate that the cell was accepted and another to indicate that the cell was dropped due to, say, buffer overflow. it is also possible that the cell was dropped inside the qse fabric due to say a collision with another cell. the qse classifies lost cells as due to one of three causes (collision, all possible outputs dead, or parity errors) and will generate an "ack information packet" back to the source to communicate this event. in each qse, the 4 bit pattern in the information packet can be independently software configured for each of the three cases. note that since each qse can be separately programmed, the patterns can even be setup so that the source knows where the cell was dropped. the information provided by the "ack information packets" can be used by the device injecting cells into the first qse stage to decide how to handle the cells; at its simplest, the device can resend cells that did not get through (a more sophisticated algorithm might also take into account where the cell was lost and the behavior of the evil twin algorithm to decide when to resend the cell; for example if the cell was dropped due to output congestion it might make sense to back off on cells to that output). for unicast traffic, part of switch bandwidth will be used to resend cells that did not make it through the first time around. this implies that sustained throughput is less than peak switching capacity. the amount of bandwidth required for resending cells and the effect of resending on latency and "cell delay variation (cdv)" has been exten- sively studied with analytical models of the fabric. these results have then been cross checked with results from simulating software models of the fabric. this data is crucial for designing fabrics that can efficiently support
pmc-sierra, inc. pm73488 qse long form data sheet pmc-980616 issue 3 5 gbit/s atm switch fabric element released datasheet 14 guaranteed "quality of service (qos)" requirements. the recommended qse fabric configurations for high quality switching takes these results into account; for example the 3 stage 160 gb/s sustained throughput fabric has a peak capacity of 256 gb/s (60% margin). the qse fabric is store-and-forward for multicast traffic. cell replication is performed in an optimal tree based manner where replication is done as far downstream as possible and each qse contains cell buffers to buffer multicast cells. a multipriority backpressure feedback is used to control the flow of multicast cells through the fabric. features switching algorithm ? supports blocking resolution in the switch fabric. ? guarantees a lower bound on switch performance using a patented randomization algorithm called evil twin switching. ? determines routes using specified bits in the header (self-routing switch fabric) for unicast traffic. ? determines output groupings using a lookup table for multicast traffic. ? allows output ports to be combined in groups of 1, 2, 4, 8, 16, or 32 for unicast traffic. ? allows output ports to be combined in groups of 1, 2, or 4 for multicast traffic. multicast support ? supports optimal tree-based multicast replication in the switch fabric. ? supports 512 internal multicast groups, expandable to 256k with external sram. ? provides 64 internal cell buffers for multicast cells. diagnostic/robustness features ? checks the header parity. ? counts tagged cells. ? checks for connectivity and stuck-at faults on all switch fabric interconnects. i/o features ? provides 32 switch fabric interfaces with integrated phase aligner clock recovery circuitry. ? provides a start-of-cell (soc) output per four switch element interfaces. ? provides an external 8-bit synchronous sram (ssram) interface for multicast group expansion. ? provides a demultiplexed address/data cpu interface. ? provides an ieee 1149.1 (jtag) boundary scan test bus. physical characteristics ? 3.3 v supply voltage. ? 5 v tolerant inputs. ? 596-pin enhanced plastic ball grid array (epbga) package. ? operates from a single 66 mhz clock.
pmc-sierra, inc. pm73488 qse long form data sheet pmc-980616 issue 3 5 gbit/s atm switch fabric element released datasheet 15 figure 1 shows a qse system block diagram. figure 1. qse interface block diagram multicast ssram (optional) host interface qse pm73488 se_soc_in(0) data from qrts or qses input ports 0 nack to qrts or qses se_soc_in(31) data from qrts or qses input ports 31 nack to qrts or qses se_soc_out(7) data to qrts or qses output ports 28:31 nack from qrts or qses se_soc_out(0) data to qrts or qses output ports 0:3 nack from qrts or qses control or data signals acknowledgment signal key:
pmc-sierra, inc. pm73488 qse long form data sheet pmc-980616 issue 3 5 gbit/s atm switch fabric element released datasheet 16 1 how the qse fits into your system the qse, together with the qrt, supports a wide range of high-performance atm switching systems. these sys- tems range in size from 5 gbps to 160 gbps. the systems can be developed to provide scalability with linear cost. another key feature of the qse/qrt architecture is that it is exceptionally fault-tolerant, both in the switch fabric and the utopia interface. this section contains a quick overview of the qse and several example applications: ? a 5 gbps switch using pm73487s and a pm73488, ? a 10 gbps switch using pm73487s and pm73488s, ? a switch architecture using pm73487s and pm73488s that scales from 5 gbps to 20 gbps, ? a switch architecture using pm73487s and pm73488s that scales from 5 gpbs to 160 gbps 1.1 qse system overview the qse is switch element, combinations of which allows switch fabric implementations that span from 5 gbps to 160 gbps. the bandwidth of a single qse is 5gbps of sustainable bandwidth; the raw, or peak, bandwidth is 8gbps. (thus the qse has an in-built speed-up factor of 8/5 = 1.6.) the qse has 32 input ports and 32 output ports. each port is a 66 mhz 6-bit interface, out of which 4 are data and 2 are control. each port can be connected to another qse or qrt. figure 2 shows a qse connected to a qrt. figure 2. qse system overview physical and/or adaptation layers qrt (pm73487) qse (pm73488) input cell sdram output cell sdram multicast sram receive feedback receive nibble data transmit nibble data transmit feedback receive utopia level 2 interface transmit utopia level 2 interface control ssram
pmc-sierra, inc. pm73488 qse long form data sheet pmc-980616 issue 3 5 gbit/s atm switch fabric element released datasheet 17 1.2 32 x 32 switch application (5 gbps) figure 3 shows a basic 32 32 switch application (5 gbps) using one qse and eight qrts. 1.3 64 x 64 switch application (10 gbps) figure 4 shows a 64 64 switch application (10 gbps) using 6 qses and 16 qrts. this application uses qses in a 3-stage fabric. this sized system can be implemented in a single 19 inch rack. figure 3. 32 x 32 switch application (5 gbps) figure 4. 64 x 64 switch application (10 gbps) qrt #1 (pm73487) receive input qrt #8 (pm73487) receive input qse (pm73488) 4 4 622 mbps aggregate 622 mbps aggregate receive utopia level 2 qrt #1 (pm73487) transmit output qrt #8 (pm73487) transmit output 4 4 622 mbps aggregate 622 mbps aggregate transmit utopia level 2 qrt #1 (pm73487) receive input qrt #8 (pm73487) receive input qse (pm73488) 4 622 mbps aggregate receive utopia level 2 qrt #1 (pm73487) transmit output qrt #8 (pm73487) transmit output 4 622 mbps aggregate qrt #9 (pm73487) receive input qrt #16 (pm73487) receive input 4 qrt #9 (pm73487) transmit output qrt #16 (pm73487) transmit output transmit utopia level 2 qse (pm73488) qse (pm73488) qse (pm73488) qse (pm73488) qse (pm73488) 622 mbps aggregate 622 mbps aggregate receive utopia level 2 622 mbps aggregate 16 16 16 16 4 transmit utopia level 2 622 mbps aggregate 622 mbps aggregate 622 mbps aggregate
pmc-sierra, inc. pm73488 qse long form data sheet pmc-980616 issue 3 5 gbit/s atm switch fabric element released datasheet 18 1.4 5 gbps to 20 gbps application example - seamless growth figure 5 illustrates the modularity of the qse and qrt architecture. a 5 gbps system can immediately be created (as shown in figure 5 ), then be upgraded to 10 gbps (as shown in figure 6 ), or 20 gbps (as shown in figure 7 on page 19 ) with the qse and the qrt. since systems composed of the qses and qrts are based on a single-stage switch fabric, the per-port cost for each system will remain the same. figure 5. 5 gbps atm switch using 8 qrts, and 1 qse figure 6. 10 gbps atm switch using 16 qrts, and 2 qses switch card ? one qse (pm73488s) eight 155 mbps interfaces port card ? two qrts (pm73487s) eight 155 mbps interfaces eight 155 mbps interfaces eight 155 mbps interfaces port card ? two qrts (pm73487s) port card ? two qrts (pm73487s) port card ? two qrts (pm73487s) switch card ? one qse (pm73488) ? ? ? eight 155 mbps interfaces port card 1 ? two qrts (pm73487s) eight 155 mbps interfaces port card 8 ? two qrts (pm73487s) switch card ? one qse (pm73488)
pmc-sierra, inc. pm73488 qse long form data sheet pmc-980616 issue 3 5 gbit/s atm switch fabric element released datasheet 19 figure 7. 20 gbps atm switch using 32 qrts, and 4 qses ? ? ? eight 155 mbps interfaces port card 1 ? two qrts (pm73487s) eight 155 mbps interfaces switch card ? one qse (pm73488) switch card ? one qse (pm73488) switch card ? one qse (pm73488) switch card ? one qse (pm73488) port card 16 ? two qrts (pm73487s)
pmc-sierra, inc. pm73488 qse long form data sheet pmc-980616 issue 3 5 gbit/s atm switch fabric element released datasheet 20 1.5 5 gbps to 160 gbps application example C lan-to-wan a powerful application of the qrt and qse devices is the creation of modules that can be used in a range of switches with only the interconnection changing between different sizes. atm switches from 5 gbps to 160 gbps can be realized with only two unique cards. a port card has one qrt, and a switch card has two qses. the switch fabric consists of three stages, each with 32 qses (or 16 switch cards). to plan for future scalability, the middle stage must be built-in upfront. this is a one-time cost. then, in order to scale in 5 gbps increments, one switch card and its accompanying eight port cards should be added. finer bandwidth scaling is possible by populating the additional switch card with port cards as needed (in increments of 622 mbps). with this switch fabric topology, scaling is possi- ble up to 160 gbps. once the initial middle stage cost has been incurred, the per-port cost for 5 gbps through 160 gbps systems remains constant figure 8. 5 gbps to 160 gbps switches modeled using only two cards qrt (pm73487) port card - one qrt one utopia level 2 interface switch card - two qses qse (pm73488) qse (pm73488) x32 x32 x32 x32
pmc-sierra, inc. pm73488 qse long form data sheet pmc-980616 issue 3 5 gbit/s atm switch fabric element released datasheet 21 figure 9 shows a 5 gbps atm switch using 8 port cards (8 qrts) and 17 switch cards (34 qses). the middle stage is composed of 16 switch cards. the 5 gbps bandwith is achieved by adding switch card #17 (which is depicted using two boxes: one stage 1 qse and one stage 3 qse), and eight port cards (each of which is depicted using two boxes: one for the rx input side, and one for the tx output side). lines between stage 1 and stage 2, and stage 2 and stage 3 switch cards represent two sets of wires, one to each of the qses in the middle stage switch cards. figure 9. 5 gbps atm switch port card #1 rx input 622 mbps port card #8 rx input 622 mbps switch card #17 stage 1 qse port card #1 tx output 622 mbps port card #8 tx output 622 mbps switch card #17 stage 3 qse switch card #16 switch card #2 switch card #1 x2 x2
pmc-sierra, inc. pm73488 qse long form data sheet pmc-980616 issue 3 5 gbit/s atm switch fabric element released datasheet 22 figure 10 shows a 10 gbps atm switch using 16 port cards (16 qrts) and 18 switch cards (36 qses). here, another switch card and eight port cards have been added to the 5 gbps switch depicted in figure 9. figure 10. 10 gbps atm switch port card #1 rx input 622 mbps port card #8 rx input 622 mbps port card #9 rx input 622 mbps port card #16 rx input 622 mbps switch card #17 stage 1 qse switch card #18 stage 1 qse port card #1 tx output 622 mbps port card #8 tx output 622 mbps port card #9 tx output 622 mbps port card #16 tx output 622 mbps switch card #17 stage 3 qse switch card #18 stage 3 qse switch card #16 switch card #2 switch card #1 x2 x2 x2 x2
pmc-sierra, inc. pm73488 qse long form data sheet pmc-980616 issue 3 5 gbit/s atm switch fabric element released datasheet 23 figure 11 shows a 15 gbps atm switch using 24 port cards (24 qrts) and 19 switch cards (38 qses).here, once again, another switch card and eight port cards have been added figure 11. 15 gbps atm switch port card #1 rx input 622 mbps port card #8 rx input 622 mbps port card #9 rx input 622 mbps port card #16 rx input 622 mbps switch card #17 stage 1 qse switch card #18 stage 1 qse port card #1 tx output 622 mbps port card #8 tx output 622 mbps port card #9 tx output 622 mbps port card #16 tx output 622 mbps switch card #17 stage 3 qse switch card #18 stage 3 qse switch card #16 switch card #2 switch card #1 port card #17 rx input 622 mbps switch card #19 stage 1 qse port card #17 tx output 622 mbps port card #24 tx output 622 mbps switch card #19 stage 3 qse x2 x2 x2 x2 x2 x2 port card #24 rx input 622 mbps
pmc-sierra, inc. pm73488 qse long form data sheet pmc-980616 issue 3 5 gbit/s atm switch fabric element released datasheet 24 figure 12 shows a 20 gbps atm switch composed of 32 port cards (32 qrts) and 20 switch cards (40 qses). by adding additional sets of a switch card and eight port cards in the same manner, this system can scale up to 160 gbps. figure 12. 20 gbps atm switch port card #1 rx input 622 mbps port card #8 rx input 622 mbps port card #9 rx input 622 mbps port card #16 rx input 622 mbps switch card #17 stage 1 qse switch card #18 stage 1 qse port card #1 tx output 622 mbps port card #8 tx output 622 mbps port card #9 tx output 622 mbps port card #16 tx output 622 mbps switch card #17 stage 3 qse switch card #18 stage 3 qse switch card #16 switch card #2 switch card #1 port card #17 rx input 622 mbps port card #24 rx input 622 mbps port card #25 rx input 622 mbps port card #32 rx input 622 mbps switch card #19 stage 1 qse switch card #20 stage 1 qse port card #17 tx output 622 mbps port card #24 tx output 622 mbps port card #25 tx output 622 mbps port card #32 tx output 622 mbps switch card #19 stage 3 qse switch card #20 stage 3 qse x2 x2 x2 x2 x2 x2 x2 x2
pmc-sierra, inc. pm73488 qse long form data sheet pmc-980616 issue 3 5 gbit/s atm switch fabric element released datasheet 25 2 theory of operation multiple pm73488 qses can be combined to build a scalable switch fabric. the qse switches data in the form of 118 nibble cells. the qse has 32-input ports and 32 output ports, each containing a nibble-wide data interface, an soc signal, and a backpressure/data-acknowledge signal. groups of 1, 2, 4, 8, 16, or 32 ports can be internally configured to act as a single aggregate port (also called gang) for unicast traffic. for multicast traffic, inputs and outputs can be grouped together in groups of 1, 2, or 4 ports. the input multicast grouping mode, output multicast grouping mode, and the unicast grouping modes do not need to be the same. also, the qse can be configured as a single 32 input 32 output switch the cell flow through the qse has two separate data paths; one path for unicast cells and another path for multicast cells. unicast cells are routed from one end of the switch fabric to the other end in a single cell time. in other words, no unicast cells are ever stored in the switch fabric. unicast cells are stored only at the ingress and egress of the switch fabric. multicast cells are routed in a store-and-forward manner. each qse can store up to 64 multicast cells. the qrt used as an interface to a switch fabric constructed with qses allows the construction of an atm switch up to 160 gbps. a diagram of the qse cell flow is shown in figure 13. the unicast cell flow contains a routing stage that uses routing information from the cell header to determine the output group. the multicast cell flow contains an interface to an external ssram that contains the multicast port vector (mpv) information for routing cells to multiple output groups. figure 13. basic qse flow external ssram arbiter unicast routing and distribution path multicast path phase aligners and receive se_d_in and se_soc_in data drivers phase aligners and receive bp_ack_in bp_ack drivers forward cell flow backpressure/ack flow miscellaneous signals
pmc-sierra, inc. pm73488 qse long form data sheet pmc-980616 issue 3 5 gbit/s atm switch fabric element released datasheet 26 2.1 phase aligners phase aligners aid in constructing large systems. clock information is recovered from the data sent to each qse switch fabric port. phase aligners are used on the bp_ack_in(31:0), se_soc_in(31:0), and se_d_in(31:0, 3:0) signal lines. since there is no setup or hold time requirements on these signals, the overall clock distribution scheme within the system can be simplified. however, overall system jitter and skew between signals on the same switch fab- ric data port must still be managed. 2.2 data drivers another aid to constructing large systems is an elastic store at each qse input data port. the data elastic store allows data arriving from different ports to be offset by up to a maximum of eight clock cycles. the internally generated and software programmable local cell_start signal marks the end of an 8-clock-period window within which the soc marker on each of the se_soc_in(31:0) lines must arrive. 2.3 unicast routing and distribution each of the 32 nibble-wide inputs is connected to an output by a crossbar. this crossbar is transparently controlled by the cells routing tag, which specifies the input-to-output connection. in the event of a conflict for an output port, higher priority cells are given preference over lower priority cells. there are three unicast cell priorities: high, medium, and low. the gang of 32, also known as distribution mode, is a special unicast routing mode in which incoming unicast cells are routed to outputs using pmcs patented congestion-minimization (evil twin switching) algorithm. in this mode, no routing information is used from the cells routing tag. depending on the gang mode, the qse will need a number of routing bits to determine the output gang of a unicast cell. for example, in gang mode of four, there are eight output gangs, thus three routing bits are required for selecting the qse. however, in distribution mode no routing bits are needed. the routing bits are taken from the head of the routing tag and are then shifted back in at the tail (which preserves header parity). this allows the next set of routing bits to be always accessible at the same spot in the tag, namely the head. the cell routing tag is broken into eight nib- bles, namely tag_0 through tag_7. figure 14 on page 27 shows the tag rotation for gang mode of four (three routing bits are used by the qse from tag_0 and then shifted back in at the tail of tag_7). tag_0 is broken up and part of it ended up at the end of tag_7 (shown by the white area in figure 14 on page 27 ). as a result, all the other tags (tag_1 through tag_7) also get broken up and shifted (as shown by the light and dark gray areas of figure 14 on page 27 ).
pmc-sierra, inc. pm73488 qse long form data sheet pmc-980616 issue 3 5 gbit/s atm switch fabric element released datasheet 27 2.4 multicast cell flow there are 64 internal cell buffers for multicast traffic. these buffers are shared among three multicast priorities: high, medium, and low. these 64 buffers are grouped into two sets of 32-cell buffers each. one set is dedicated to ports 0 to 15, the other set to ports 16 to 32. a multicast queue engine dynamically allocates the cell buffers to incoming multicast cells. each cell is buffered until it can be sent out on all output ports to which it should be routed. these output ports are designated by a multi- cast group vector (mgv) that is associated with a multicast group index (mgi) carried by each multicast cell. each qse holds multicast mgvs in an mgv ram. the qse has internal ram to support up to 128 mgvs. this support can be extended up to 256k mgvs by using an external mgv ram. each multicast cell contains the ram address of the mgv it is supposed to use. when a multicast cell is received, its mgv is fetched from ram and copied to the multicast_queue_completion register. the multicast_queue_completion register tracks to which qse ports the cell needs to be sent before its cell buffer can be cleared. in a multistage qse fabric, each multicast cell will look up mgvs at each qse. the mgvs sequence determines which output ports will finally receive the cell. the mgv structure allows software to create an optimal distribution tree for each multicast cell. multicast operation can be best understood by considering the qse multicast path as two separate engines; the multi- cast queue engine and the multicast dequeue engine. the multicast queue engine queues cells into the multicast cell buffers (of which there are 64), and issues backpressure on the bp_ack_out(31:0) lines. the multicast dequeue engine selects and dequeues cells from the buffers for output ports as guided by the backpressure received on the bp_ack_in(31:0) lines. figure 14. routing bits rotation for unicast traffic, gang mode of four bit mapping tag_1 tag_2 tag_3 tag_4 tag_5 tag_6 tag_7 tag_1 tag_2 tag_3 tag_4 tag_5 tag_6 tag_7 tag_0 32 10 32 10 tag_0
pmc-sierra, inc. pm73488 qse long form data sheet pmc-980616 issue 3 5 gbit/s atm switch fabric element released datasheet 28 2.4.1 multicast queue engine the multicast queue engine associates input ports with cell buffers, computes backpressure for the input ports, and stores incoming cells into the buffers. in doing so, it guarantees: ? no input port will have more than three cells pending in the qse this can be changed to allow four pending cells by setting the allow 4 bits per port bit (bit 1) in the bp control register. ? no input port will have more than two high-priority cells pending. ? the sum of low- and medium-priority cells pending from any single input port will be less than 2. in addition, the queue engine allows buffers to be reserved for high-priority cells or high/medium-priority cells. this is controlled by bits 2 and 3 of the bp_control_register (refer to section 9.3.29 bp_control_register on page 109 ). the four possible combinations for these two bits are listed in table 1. the multicast queue engine will compute backpressure for the preceding qse/qrt to ensure the constraints listed in table 1 are satisfied. the same reservation policy applies to both sets of 32 buffers. after the mgv address for the cell enters the qse, the mgv associated with that cell is fetched and loaded into the queue_completion_register (an internal register) as soon as possible. 2.4.2 multicast dequeue engine in each cell time, the multicast dequeue engine selects one multicast cell for each of the 32 output ports. in effect, all multicast cells wanting to go to a particular output port arbitrate among themselves to select the most appropriate port. arbitration occurs independently for all 32 ports. the cells winning the internal multicast arbitration then com- pete with the incoming unicast cells for access to the output ports. multicast arbitration winners are chosen to satisfy the following conditions in this sequence: ? obey backpressure from the down stream qse or qrt. only cells with the allowed priorities will take part in arbitration. ? higher priority cells win over lower priority cells. ? cells that came in earlier win over cells that came in later (if they have the same priority). ? if multiple cells have the same priority and came in simultaneously, cells from a random input gang group will be selected. ? if multiple cells have the same priority, came in simultaneously, and belong to the same input gang group, the cell with the lowest port number will be selected. ? ties are broken randomly. table 1. bp_control_register; threshold control bits for each set of 32 buffers bit 3 bit 2 description 00 ? four buffers are reserved for high-priority cells. ? four buffers are reserved for high- or medium-priority cells. ? all other buffers can be used by any cell. 0 1 ? four buffers are reserved for high-priority cells. ? all other buffers can be used by any cell. 1 0 ? eight buffers are reserved for high- or medium-priority cells. ? all other buffers can be used by any cell. 1 1 ? all buffers can be used by any cell.
pmc-sierra, inc. pm73488 qse long form data sheet pmc-980616 issue 3 5 gbit/s atm switch fabric element released datasheet 29 this arbitration occurs among all cells in the cell buffers and occurs for all 32 ports. in effect, arbitration occurs for output ports in sequence, starting with cells arbitrating for port 0, then for port 1, and continuing on until port 31 (even though the actual implementation uses a parallel algorithm). multicast cells that have won this arbitration then compete with unicast cells for access to the output ports. in this contention, the cell with the highest priority wins and ties are broken randomly according to the programmable ratio set in the uc/mc_fairness_register (refer to section 9.3.6 uc/mc_fairness_register on page 97 ). all these operations are optimized so that, in the absence of congestion, it is possible for a multicast cell to leave the qse in the cell time immediately after it arrived. as mentioned before, the queue completion register (32-bit vector) indicates the outputs to which each multicast cell needs to go. as a cell goes out on its desired outputs, the appropriate bits in the queue completion register are cleared. when all bits in the queue completion register have been cleared, the cell is deleted from the internal buffers and the buffer is reused for new incoming traffic.
pmc-sierra, inc. pm73488 qse long form data sheet pmc-980616 issue 3 5 gbit/s atm switch fabric element released datasheet 30 figure 15 shows an example of a high-priority cell preempting a cell in the multicast queue, and the resulting bit set- tings in the multicast_queue_completion_register (an internal register). (for the sake of simplicity, only 8 of the 32 outputs, and eight bits of the mgv_register (refer to section 9.3.4 multicast_group_vector_register on page 96 ) and multicast_group_completion_register (an internal register) are shown.) 2.5 arbiter the arbiter selects between unicast cells and multicast cells contending for the same output port. higher priority cells are given preference over lower priority cells. if a multicast cell and unicast cell have the same priority, one cell is randomly chosen. the random choice can be biased in favor of either unicast cells or multicast cells at different points in the switch fabric by using the uc/mc_fairness_register (refer to section 9.3.6 uc/ mc_fairness_register on page 97 ). in general, unicast cells should be favored at later stages in the switch fabric. favoring unicast cells is necessary in multiple-stage switch fabrics since unicast cells are routed in a cut- through fashion and multicast cells are routed in a store-and-forward fashion. as such, a unicast cell becomes more valuable as it proceeds further in the switch fabric, since it did so at the expense of other cells. figure 15. example of multicast cell handling in the qse output(0) output(1) output(2) cell_m output(3) cell_h output(4) output(5) cell_m output(6) output(7) multicast queue 0 0 1 1 0 1 0 0 0 7 cell_m 0 0 1 0 0 1 0 0 multicast_queue_completion_register (records if the cells arrived at the destinations indicated in the multicast_group_vector_register.) 0 7 high-priority cell cell_h this bit is not set since a higher priority cell was output on output(3), preempting the cell in the multicast queue. multicast group vector (mgv) (specifies where cells should be sent.)
pmc-sierra, inc. pm73488 qse long form data sheet pmc-980616 issue 3 5 gbit/s atm switch fabric element released datasheet 31 for example, consider a congested 3-stage switch fabric where unicast cells and multicast cells of equal priorities col- lide at each stage in the fabric, without any biasing. a unicast cell must make it from ingress to egress in one cell time and the chances of doing so would be a little more than (1/2) 3 = 12.5%. however, each multicast cell would have a 50% chance of advancing to the next stage in the switch fabric. 2.6 bp_ack drivers the bp_ack_out(31:0) lines are used to send information from a qse to upstream qses or qrts. these lines are used to send two types of information: ? backpressure information (for unicast cells). ? transmit acknowledge information (for multicast cells). backpressure information is sent for multicast cells. this information indicates to an upstream qrt or qse if the qse can accept another multicast cell in the next cell time. backpressure information also indicates what multicast cell priorities the qse can accept. cell transmit acknowledge information is sent for unicast cells. this information signals whether or not the unicast cell transmitted in the current cell time made it to its destination qrt. if the cell makes it to the destination qrt, an acknowledgment (ack) is sent. if the cell has been dropped in the switch fabric, information is sent back indicating if the cell was dropped internally mid switch negative acknowledgment (mnack) or at the output of the switch fabric output negative acknowledgment (onack). the mnack and onack is used by the qrt to determine when to retry sending the given cell. 2.7 interdevice interconnectability all input and output ports can be configured in groups of four to directly connect to either qrt devices or other qse devices. this allows considerable flexibility in the switch fabric types and sizes that can be constructed using the entire pmc chip set. 2.8 network topologies and the speedup factor (sf) for many switch fabric architectures using the qse, a single metric called the speedup factor (sf) allows compari- son of different network topologies, which is independent of traffic load and type. the sf also allows for predictions about the network performance. before describing the sf metric, we will briefly discuss the network philosophy and the different network topologies.
pmc-sierra, inc. pm73488 qse long form data sheet pmc-980616 issue 3 5 gbit/s atm switch fabric element released datasheet 32 2.8.1 network philosophy given current technology, to scale through 160 gbps, a network must be distributed and use buffers at the network inputs and outputs. in an ideal world, crossbars of any arbitrary size could be built to provide connectivity for the net- work inputs and outputs. additionally, there would be a central brain, or global arbiter, to control the input buffers and schedule cells optimally for routing in the network, as shown in figure 16. unfortunately, given real constraints, it is not possible to have a global arbiter wired to each input that has knowledge of all cells in the system, and can quickly make optimal decisions about routing. thus, each input must make deci- sions using knowledge local to its buffers. this results in the possibility of collisions at the network outputs, even though it is a perfect crossbar, as shown in figure 17. figure 16. ideal distributed network figure 17. more realistic distributed network perfect crossbar input buffers output buffers global arbiter perfect crossbar input buffers output buffers local arbiters output collision
pmc-sierra, inc. pm73488 qse long form data sheet pmc-980616 issue 3 5 gbit/s atm switch fabric element released datasheet 33 replacing the idealized crossbar with a buildable, traditional banyan network increases the possibility of internal net- work collisions, as shown in figure 18. given a particular banyan network, one can always find a large class of traf- fic patterns that will cause many internal collisions. for large banyan networks, the collision problem is greatly increased. to reduce internal collisions in the traffic-dependent banyan networks, the qrt/qse network adds a distribution/ randomizing network (shown in figure 19) that uses a patented intelligent configuration algorithm, known as evil twin switching. the algorithm (described in section 2.8.3 speedup factor (sf) on page 36 ) allows lower-bound- ing the network performance, independent of traffic patterns. figure 18. large distributed network (will not work well with banyan alone) figure 19. high-level qrt/qse system banyan input buffers output buffers output collision internal collisions local arbiters banyan input buffers output buffers internal collisions intelligent configuration algorithm and randomizer local arbiters
pmc-sierra, inc. pm73488 qse long form data sheet pmc-980616 issue 3 5 gbit/s atm switch fabric element released datasheet 34 to overcome the inefficiencies caused by collision in the network, the fabric must be run at a rate greater than line rate. the speedup factor is the minimum rate necessary to guarantee that the network is no longer the system bottle- neck. note that in this case, the network efficiently moves data from the input to the output buffers, and the switch performs similar to a purely output buffered switch. 2.8.2 network definition a large range of switch fabrics can be described as follows: w ith the following notation: p refers to the number of fabric planes, and x, y, and z refer to the routing tag size necessary to make routing decisions in the banyan section of the network to route cells to the correct output port. this is summarized as follows: (z)xp 1-stage network (y,z)xp 3-stage network hence, the (3) 1 network shown in figure 20 refers to a single switch stage, and three routing bits are required to select from one of the eight output port groupings. (recall that the qse has 32 output ports that can be configured in groups of 1, 2, 4, 8, 16, or 32. in figure 20, they are configured in groups of four. the input and output buffers pro- vided by the qrt have four input ports and four output ports to the switch fabric, and are logically broken into the input half of the qrt (irt) and output half of the qrt (ort) for convenience. the (5) 4 network shown in figure 21 is an example of a network with four parallel planes. it demonstrates the flex- ibility allowed because the qrt has four input and output ports. in this case, randomization is performed in the irt. figure 20. (3) x 1 - 5 gbps system figure 21. (5) x 4 - 20 gbps system x4 622 mbps utopia 622 mbps utopia qse ort irt x 4 x 4 x4 x 1 622 mbps utopia 622 mbps utopia qse ort irt x 4 x 4 x 1 randomizer
pmc-sierra, inc. pm73488 qse long form data sheet pmc-980616 issue 3 5 gbit/s atm switch fabric element released datasheet 35 in figure 22, the first stage of qses is configured to provide the required randomization, and the next two switch stages route the cells to the final port destination. the second qse stage needs only to make an up or down deci- sion requiring a single routing bit, while the third qse stage needs to select between eight qrts, requiring three rout- ing bits. figure 22. (1,3) x 1 - 10 gbps system x 16 x 16 x16 x 16 622 mbps utopia x 4 622 mbps utopia qse irt x 4 qse ort x 4 qse qse qse qse x 4 randomizer
pmc-sierra, inc. pm73488 qse long form data sheet pmc-980616 issue 3 5 gbit/s atm switch fabric element released datasheet 36 2.8.3 speedup factor (sf) if the traffic pattern presented to a particular banyan network results in many internal collision, a shuffling pattern exists that has been proven to result in few internal collisions. although a purely random reshuffling results in good behavior, we can lower-bound network performance by using randomization along with the evil twin switching algorithm as shown in figure 23. this algorithm is as follows: randomly choose a configuration, route data, choose the dual or evil twin switching configuration, route data, and repeat. this algorithm minimizes the number of inter- nal collisions. in 3-stage networks, the first stage of the qses provide this functionality. even with a perfect crossbar for a network, there are still output collisions, and despite the evil twin switching algo- rithm, there are still internal collisions (albeit fewer). thus, multiple routing attempts must be made per cell to yield full throughput. this can be accomplished by running the switch fabric at a faster clock rate than the buffering logic. figure 23. randomizer (with evil twin switching algorithm) figure 24. network needs to be run faster than the line rate banyan input buffers output buffers local arbiters mnack intelligent configuration algorithm and randomizer onack randomly choose configuration send data choose the dual or evil twin switching configuration send data input buffers output buffers local arbiters
pmc-sierra, inc. pm73488 qse long form data sheet pmc-980616 issue 3 5 gbit/s atm switch fabric element released datasheet 37 the chance for internal collisions increases as the network load increases, and the exact behavior varies with network topology. an example of this behavior is shown in figure 25 and the sf is inferred from the limiting case where the network is fully loaded. given this notion of sf, how much faster is fast enough? theoretical models and simulations can answer that ques- tion. given that the switch fabric can be run at a certain clock rate relative to the buffering logic, we can know which networks to choose to prevent the network from becoming a bottleneck. table 2, table 3 show all of the 1-, 3-stage network topologies requiring an sf of less than 1.6, which is the maxi- mum speedup allowed by the actual implementation. figure 25. definition of the speedup factor figure 26. how to use the sf to select favorable networks 1 p a = probability of cell acceptance limiting case, where the load = 1, sf = 1/ p a 01 p a load network topology 2.0 160 gbps network size speedup factor (sf) fabric rate 622 mbps 1.0
pmc-sierra, inc. pm73488 qse long form data sheet pmc-980616 issue 3 5 gbit/s atm switch fabric element released datasheet 38 table 2. speedup factor (1-stage networks) network size (gbps) speedup factor (sf) number of qses (3) 1 5 1.22 1 (4) 2 10 1.36 2 (5) 4 20 1.57 4 table 3. speedup factor (3-stage networks) network size (gbps) speedup factor (sf) number of qses (1,3) 110 1.28 6 (1,4) 220 1.41 12 (2,3) 120 1.32 12 (2,4) 240 1.46 24 (3,3) 140 1.39 24 (3,4) 280 1.53 48 (4,3) 180 1.49 48
pmc-sierra, inc. pm73488 qse long form data sheet pmc-980616 issue 3 5 gbit/s atm switch fabric element released datasheet 39 3 external port descriptions 3.1 switch fabric port and interface description each port is a 6-bit interface consisting of: ? a nibble-wide data interface (se_d_in and se_d_out), ? an soc signal (se_soc_in and se_soc_out), and ? a backpressure/data acknowledge signal (bp_ack_in and bp_ack_out). 3.1.1 se_soc encodings the se_soc encodings (se_soc_in(31:0), se_soc_out(7:0)) provide guaranteed transitions and soc encod- ings. the se_soc signals carry a repeating four 0s and four 1s pattern to guarantee transitions required by the phase aligner. the soc signal on data lines associated with an se_soc line is indicated by a break in this repeating pat- tern. the soc is a single 1 followed by five 0s. figure 27 shows the guaranteed transitions. figure 28 provides an expanded view of the signal transitions and the first nibble after the soc pulse (nibble #0) corresponds to nibble 0 in table 5 on page 40 . figure 27. se_soc encodings figure 28. expanded se_soc encodings four 1s four 0s five 0s four 1s four 0s four 1s four 0s start of cell pulse se_clk se_soc #115. #116 #117 #0 #1 four 1s four 0s one five 0s four 1s tsesu tseho tsesu start of cell pulse magnified se_clk se_data magnified se_soc
pmc-sierra, inc. pm73488 qse long form data sheet pmc-980616 issue 3 5 gbit/s atm switch fabric element released datasheet 40 3.1.2 data cell format the regular cell format is shown in table 5. table 5. regular cell format nibble symbol definition comment 0 pres(1:0), mc, sp pres = 10 b : cell present. 01 b : cell not present (see table 6 on page 41 ). 00 b : cell assumed to be not present (failure). 11 b : cell assumed to be not present (failure). mc = 1 b : multicast cell. sp spare bit. the spare bit is not interpreted or used by the qse. 1 sp(1:0), priority(1:0) sp(1:0) spare bits. priority = 11 b : high-priority cell. 10 b : medium-priority cell. 01 b : low-priority cell. 00 b : undefined. cell discarded by qse. priority for the switching fabric. the qrt should be configured never to generate priority 00 b cells, since they are discarded by the qse. the spare bits are not interpreted or used by the qse. 2 tag_0 routing tag 0 or multicast_group_index(15:12). refer to section 9.3.3 multicast_group_index_register on page 96 . 3 tag_1 routing tag 1 or multicast_group_index(11:8). refer to section 9.3.3 multicast_group_index_register on page 96 . 4 tag_2 routing tag 2 or multicast_group_index(7:4). refer to section 9.3.3 multicast_group_index_register on page 96 . interpretation of tag_5:0 depends on whether or not the cell is a multicast cell. 5 tag_3 routing tag 3 or multicast_group_index(3:0). refer to section 9.3.3 multicast_group_index_register on page 96 . 6 tag_4 routing tag 4 or multicast_group_index(23:20). currently, qse supports only 256k multicast group vectors, i.e. it only uses multicast group index(17:0). therefore, bits 23:20 are ignored. 7 tag_5 routing tag 5 or multicast_group_index(19:16). refer to section 9.3.8 multicast_group_index_msb on page 98 . currently, qse supports only 256k multicast group vectors, i.e. it only uses multicast group index(17:0). therefore, bits (19:18) are ignored. 8 tag_6 routing tag 6.
pmc-sierra, inc. pm73488 qse long form data sheet pmc-980616 issue 3 5 gbit/s atm switch fabric element released datasheet 41 the idle cell format is shown in table 6. the idle cell format is chosen to make the interface robust to both stuck-at faults, as well as bridging faults on the data lines. 9 tag_7 routing tag 7. 10 outchan_3 interpreted as outchan(15:12) by a qrt. not used by the qse. 11 sp(1:0), mb, parity sp(1:0) spare bits. mb mark bit: cells that are present and have this bit set are counted by the input_marked_cell_count (refer to section 9.3.11 input_marked_cells_count on page 99 ) and output_marked_cell_count (refer to section 9.3.12 output_marked_cells_count on page 99 ) counters. p should be odd parity over nibbles 0 to 11. 12 outchan_2 interpreted as outchan(11:8) by a qrt. not used by the qse. 13 outchan_1 interpreted as outchan(7:4) by a qrt. not used by the qse. 14 outchan_0 interpreted as outchan(3:0) by a qrt. not used by the qse. 15 vci_3 interpreted as virtual channel identifier (vci)(15:12) by a qrt. not used by the qse. 16 vci_2 interpreted as vci(11:8) by a qrt. not used by the qse. 17 vci_1 interpreted as vci(7:4) by a qrt. not used by the qse. 18 vci_0 interpreted as vci(3:0) by a qrt. not used by the qse. 19 pti(2:0)/clp interpreted as the payload type indicator (pti) and cell loss priority (clp) fields from the cell by a pm73487a. not used by the qse. 20 seq_1 interpreted as seq(7:4) by a qrt. not used by the qse. 21 seq_0 interpreted as seq(3:0) by a qrt. not used by the qse. 22-117 payload interpreted as 48 bytes of atm cell payload by a qrt. not used by the qse. table 6. pm73488 mode idle cell format nibble symbol definition comment 0 pres(3:0) pres = 0100 b : cell not present. 1 idle_0 idle_0 = 0000 b : all 0. 2 idle_1 idle_1 = 1000 b : marching 1 pattern, which protects against bridging faults. table 5. regular cell format (continued) nibble symbol definition comment
pmc-sierra, inc. pm73488 qse long form data sheet pmc-980616 issue 3 5 gbit/s atm switch fabric element released datasheet 42 3.1.3 bp_ack encodings the bp_ack encodings (bp_ack_in and bp_ack_out) guarantee transitions, and bp and ack encodings are shown in figure 29. the bp_ack signal is used to signal backpressure/cell acknowledgment to the previous stage. to ensure the transi- tions required by the phase aligner, this line carries a repeating four 0s and four 1s pattern. the actual informa- tion is transferred by a break in this pattern (shown by bp_ack signaling in figure 29). the pattern break is identified by a bit inversion (inversion 1) on the line, followed by a mode, and two data bits, followed by a second inversion (inversion2) of the expected bit, if the previous pattern had continued. this is followed by the last two bits. after these information bits, the repeating pattern restarts with four 0s. 3 idle_2 idle_2 = 0100 b : marching 1 pattern, which protects against bridging faults. 4 idle_3 idle_3 = 0010 b : marching 1 pattern, which protects against bridging faults. 5 idle_4 idle_4 = 0001 b : marching 1 pattern, which protects against bridging faults. 6 idle_5 idle_5 = 0000 b : 7 idle_6 idle_6 = 0000 b . 8-15 reserved (qse currently outputs 0000 b .) 16-117 unused (qse currently outputs 0000 b .) figure 29. bp_ack encodings table 6. pm73488 mode idle cell format (continued) nibble symbol definition comment four 1s four 0s four 1s four 0s four 0s four 1s inversion 1 mode data3 data2 inversion 2 data1 data0 se_clk bp_ack base pattern bp_ack signaling
pmc-sierra, inc. pm73488 qse long form data sheet pmc-980616 issue 3 5 gbit/s atm switch fabric element released datasheet 43 the information bits encoding is described in table 7. 3.2 data acknowledge the data acknowledge signals (bp_ack_in and bp_ack_out) are used to indicate if, at the current cell time, a cell was successfully transmitted or not. data acknowledge is a single line per port that returns from a cells destina- tion in the reverse direction from the data flow. if the cell is being blocked by the switch, this information is gener- ated directly by the qse. if the cell is not being blocked by the switch, this information is forwarded from the next switch stage. the data acknowledge signal provides the following information to the qrt: ? the cell was successfully received by the qrt at the cell destination (ack). ? the cell was not accepted by the qrt at the cell destination (does not happen by design in the pm73487). ? the cell was blocked by the switch at the output of the switch fabric (refer to section 9.3.30 ack_payload on page 109 ). ? the cell was blocked internal to the switch fabric (refer to section 9.3.30 ack_payload on page 109 ). ? the cell was detected as a parity error cell by a qse (refer to section 9.3.30 ack_payload on page 109 ). ? the cell was headed to a gang of which all ports are dead (refer to section 9.3.31 gang_dead_ack_payload on page 110 ). thus, direct information is provided to the qrt on a per-cell basis and on a per-vc basis. the qse behavior to support the above scenario is as follows: ? if the cell was a parity errored cell, and the qse is configured to check parity in the chip_mode register (refer to the field labeled parity_check on page 95 ), then the parity acknowledge in the ack_payload register is sent (the default is onack). ? if the cell is dropped due to congestion at an output of the qse, then ack payload for cells dropped due to congestion in the ack_payload register is sent (bits3:0). refer to bits 3:0 in section 9.3.31 gang_dead_ack_payload on page 110 . table 7. information bit encoding mode data 3 data 2 data 1 data 0 description 01 = backpressure on high-priority multicast cell. 1 = backpressure on medium-priority multicast cell. 1 = backpressure on low-priority multicast cell. 0 backpressure information. this signal is present each cell time regardless of whether a cell was transmitted or not (on that link). this signal is withheld if any problem is detected on the input port. 1 0 0 0 0 unassigned. 1 0 1 0 0 signals mnack. 1 1 0 0 0 signals onack. 1 1 1 0 0 signals ack.
pmc-sierra, inc. pm73488 qse long form data sheet pmc-980616 issue 3 5 gbit/s atm switch fabric element released datasheet 44 ? if the cell was blocked at an output of the qse because the entire gang is disabled (the default is ack), then the cell is to be cleared when all ports to a qrt are known to be unavailable. ? if the cell was successfully routed through the qse, the return path is set up to route the data-acknowledge signal back from the next switch stage. for multicast traffic, the bp_ack_in and bp_ack_out signals also serve as a backpressure signal, indicating at each cell time, the multicast cell priority the qse can accept on the following cell time on a given port. 3.3 microprocessor interface the qse has a non-multiplexed, asynchronous, general-purpose microprocessor interface (pif) through which the internal registers can be accessed. the external ssram is also indirectly accessed through this same interface. 3.4 multicast sram interface the qse supports 128 internal multicast groups, and is expandable up to 256k through an external ssram. 3.5 clocks and timing signals the qse is driven from a single clock source up to a maximum clock rate of 66 mhz. to indicate the soc, there is one se_soc_in signal per input port. there is one se_soc_out signal per group of four outputs. cells must arrive at the input ports within an eight clock-cycle window. a cell_start is used as a reference for an internal cell start signal to determine the eight clock-cycle window in which the soc signal on the se_soc_in lines are valid. the internal cell start signal delay from the external cell_start signal is programmed in the cell_start_offset (refer to section 9.3.28 cell_start_offset on page 109 ). 3.6 ctrl_in ctrl_in is a one bit input port. its function depends on the value of the enable_stat_pins (bit 7) bit in the chip_mode register. when this bit is 0, ctrl_in directly sets the value of the internal no data out control bit. what this internal bit does is explained later. when this bit is 1, ctrl_in expects a data packet which sets the value of both, the internal /no data out and the /no data in registers. the format for the data packet is described below: data on this line has to be clocked out by its source at one-eighth the qse clock rate. ctrl_in is normally 0. a valid data packet starts with a 0 -> 1 transition on the line (implying that the first bit of the data packet is 1). a valid data packet starts with 100 b followed by 2 control bits and 6 bits which are ignored. if the first 3 bits of a data packet are not 100 b , the data packet is ignored (i.e. the next 8 bits are ignored). data packets may not arrive back to back. at least 4 zero bits must be present between any two data packets. a valid data packet is therefore: 100b 0 b 1 xxxxxx b . b 0 is the desired value of /no data in and b 1 is the desired value of /no data out. if the internal /no data in bit is asserted the qse will continously apply back pressure on all inputs and all priori- ties. if the internal /no data out bit is asserted the qse will behave as if all its outputs are receiving backpressure on all priorities.
pmc-sierra, inc. pm73488 qse long form data sheet pmc-980616 issue 3 5 gbit/s atm switch fabric element released datasheet 45 3.7 stat_out this is a bidirectional port whose function depends on the value of the enable_stat_pins (bit 7) bit in the chip_mode register. when this bit is 0, stat_out is configured as an input port and directly sets the value of the no data in internal register (see ctrl_in description above for what this internal register does). when this bit (enable_stat_pins) is 1, stat_out is configured as an output and periodically outputs an information packet which indicates whether the internal multicast buffers are empty. stat_out is normally 0 and the information packet generated on the stat_out pin is 5 bits long and is clocked out using the qse clock. the pattern starts with a 1 and the 5 bits are 10b 0 b 1 b 2 including the 1 that starts it all. if b 0 b 1 b 2 is 000, then it means that all the multicast buffers are empty. if b 0 b 1 b 2 is any other three-bit value, then it means that the multicast buffers are not empty. note that this packet represents the instantaneous status of the multicast buffers. therefore, if a multicast cell is entering or exiting the chip at just about the time the packet is being output, then the information in the packet must be interpreted with caution. however such delicate race condi- tions are not a problem in practice. (see fabric switch-over on page 45.) 3.8 fabric switch-over the reason /no_data_in, /no_data_out and stat_out exist is to support hitless fabric switch-over. this means that we wish to detour traffic to a back-up fabric and take the current fabric down for repairs, all without losing a single cell. this can be accomplished in several different ways. we suggest a possible scheme below. our scheme only uses the /no_data_in and stat_out features. other schemes may also use the /no_data_out feature. there are two fabrics, a and b. each fabric has two kinds of inputs: data_in and bp_ack_in. assume that these inputs are duplicated to both fabrics. each fabric also has two kinds of outputs: data_out and bpack_out. assume that there are muxes that can choose outputs either from fabric a or from fabric b. at any point in time, all muxes must select a, or all muxes must select b, i.e. all muxes must switch in lock-step. initially, we are using fabric a, and b is the back-up. thus all muxes are set to choose a. at the end of the process, we want to be using fabric b, with a being the back-up. during the process, no cell must get lost, and there should be no ordering violations. ? assert /no_data_in on both a and b. for unicast, the result is that both a and b will reject cells and return nacks. for multicast, the result is that both a and b will assert full back-pressure. of course, only the nacks and back-pressure from a will reach the ingress qrts, because the muxes are set to choose a. ? effectively, the qrt will not be able to deliver even a single cell. all unicast cells will be attempted, but they will bounce back with nacks. multicast cells cant even be attempted because of full back-pressure. ? wait for stat_out to go to "000" on all qses on both fabrics. this indicates that all multicast cells that were in transit in the fabrics have drained out. of course, only the cells from a will reach the egress qrts, because the muxes are set to choose a. ? at a cell time boundary, switch all muxes to choose b. ? now deassert /no_data_in on both a and b. cells will start flowing through b, and a can be taken down safely for maintenance/repair.
pmc-sierra, inc. pm73488 qse long form data sheet pmc-980616 issue 3 5 gbit/s atm switch fabric element released datasheet 46 3.9 cell timing/latency the data latency through each qse depends on the distribution mode. the maximum data latency is listed in table 8. the data acknowledge through each qse is a maximum of five clock cycles. table 8. data latencies aggregate mode latency 1 13 clock cycles 2, 4, 8, 16, 32 10 clock cycles
pmc-sierra, inc. pm73488 qse long form data sheet pmc-980616 issue 3 5 gbit/s atm switch fabric element released datasheet 47 4 qse feature descriptions 4.1 distribution algorithm the qse has an algorithm that allows unicast cells to take advantage of multiple paths in multistage switch fabrics. this algorithm is run simultaneously by all qses in a system. since the position (row and column) of each qse is known (refer to section 9.3.26 switch_fabric_row on page 107 and to section 9.3.27 switch_fabric_column on page 108 ), and they all receive a synchronizing strobe (cell_24_start), each qse can determine exactly what the other qses are doing. this enables the qses to act globally to minimize cell congestion in the switch fabric. 4.2 cell start offset logic each qse needs to be informed when the window occurs during which the se_soc_in is valid for the input ports. generally, since this window can vary from one qse to another in the fabric, it is made software programmable by setting the cell_start_offset register (refer to section 9.3.28 cell_start_offset on page 109 ). the significance of this register is as follows: the qse generates an internal signal called "local cell_start", which is simply a delayed version of external cell_start input, where the delay is the number of clock cycles given in the cell_start_offset register. the valid window for accepting se_soc_in is the 8-clock-cycle interval immediately preceding the pulse of local cell_start signal. (for a detailed timing diagram, see relation between external cell_start and local cell_start on page 47.) 4.2.1 relation between external cell_start and local cell_start figure 30 shows the relationship between the external cell_start signal and the local cell_start signal, which is used internally by the qse. the signal offset is programmable through the microprocessor interface (refer to section 9.3.28 cell_start_offset on page 109 ) to allow for easy system synchronization. the qse performs cut-through routing wherever possible and requires the soc to be synchronized across all input ports. for greater flexibility, the qse allows cells starting within a window of eight clock pulses to be considered valid. the end of the 8-clock-cycle window is also indicated by the local cell_start signal. figure 30. qse cell-level timing soc pulses derived from the se_soc_in signals tseau tesu cstart delay cstart delay valid soc pulses 8 clock cycles valid soc pulses 8 clock cycles clock cycle clock cycle delta delta cst high cst low se_clk external cell_start local cell_start soc pulses
pmc-sierra, inc. pm73488 qse long form data sheet pmc-980616 issue 3 5 gbit/s atm switch fabric element released datasheet 48 4.2.2 relation between local cell_start and data out of the qse the qse switch latency from the local cell_start signal to the first nibble depends on the gang mode, as shown in figure 31. the switch latency is 8 clocks from the local cell_start signal for all unicast gang modes, except for unicast gang mode = 0, in which case the switch latency is 11 clocks.. the cell_24_start signal is used as a strobe to synchronize the internal state machines of all qses and qrts in the system. when it occurs, the cell_24_start signal must be coincident with the cell_start signal and should occur every 4n th cell time. (the signal is called cell_24_start for legacy reasons that are no longer rele- vant.) 4.3 general description of phase aligners the phase aligners recover a clock from the data in the qse-to-qse, qrt-to-qse, and qse-to-qrt interfaces as shown in figure 32 on page 49 . the forward cell path consists of five signals, se_d(3:0) and se_soc, while the backward path consists of one signal, bp_ack. in the forward cell path, the phase aligners lock to the se_soc_in signal that has guaranteed signal transitions. the recovered clock is then used to sample the other signals, se_d_in(3:0). in the backward path, the phase aligners lock to the bp_ack_in signal that has guaranteed signal transitions. figure 31. qse switch latency #115. #116. #117. #0 #1 #2 #3 #115. #116. #117. #0 end of 8 clk valid window se_clk local cell_start soc pulses gang mode not = 1 se_d_out se_soc_out gang mode = 1 se_d_out(1) se_soc_out(1)
pmc-sierra, inc. pm73488 qse long form data sheet pmc-980616 issue 3 5 gbit/s atm switch fabric element released datasheet 49 4.4 multicast backpressure control as described in section 2.4.1 multicast queue engine on page 28 , the multicast queue engine computes multiprior- ity backpressure (high, medium, or low) based on the following factors: ? total buffer usage. ? buffer usage on an individual port. the buffer use constraints described therein guarantee against one port flooding the qse and choking other ports (by the per-port buffer limits) or heavy traffic from cells of a lower priority level choking cells of higher priorities (by allowing buffers to be reserved for high- and medium-priority cells). the qse is tolerant of the qrt and other qses on its input ignoring the backpressure it applies. depending on the situation, cells that arrive in violation of recommended backpressure may be dropped or may be accepted and treated as normal cells. this is fault behavior since, during normal operation, neither the qse nor the qrt will ever violate backpressure applied by a downstream qse. 4.5 multilevel reset when the reset pin is asserted, the qse is in total reset. access is not permitted to any register; and all qse-driven signals, except for ram_clk, are static at either 0 or 1. figure 32. basic forward and backward data path qrt (irt portion) b qrt (irt portion) a qse (switching matrix) qse (switching matrix) qrt (ort portion) b qrt (ort portion) a qrt-to-qse interface qse-to-qrt interface forward cell flow backward bp/ack flow qse-to-qse interface
pmc-sierra, inc. pm73488 qse long form data sheet pmc-980616 issue 3 5 gbit/s atm switch fabric element released datasheet 50 when the chip_hardware_reset bit in the chip_mode register (refer to section 9.3.2 chip_mode on page 95 ) is enabled, all registers can be read from and written to, but do not attempt to access the multicast port vec- tors in the multicast ram. the rest of the device is in full reset. when the chip_hardware_reset bit in the chip_mode register (refer to section 9.3.2 chip_mode on page 95 ) is disabled, but the sw_reset bit in the control_register (refer to section 9.3.22 control_register on page 103 ) is enabled, the processor has fast access to the multicast ram. this mode allows the multicast port vectors to be set up quickly at initialization. in normal device operation, the microprocessor has a single multicast ram access every 118 clocks.
pmc-sierra, inc. pm73488 qse long form data sheet pmc-980616 issue 3 5 gbit/s atm switch fabric element released datasheet 51 5. fault specification 5. 1. purpose the purpose of this chapter is to provide system designers with the high-level failure behavior of the system. it docu- ments the algorithms used, as well as the qrt- and qse-specific behaviors required. 5. 2. basic data and bp/ack flow the basic data path through the qrt and qse is shown in figure 33. in this example, data enters the switch through a utopia interface at the irt portion on the qrt and is queued in the irt. then, cells are played out to the switch fabric (which consists of one or more stages of qses), and finally enters the ort portion of the qrt where it is queued. cells are then played out of the switch through a utopia interface. failures within the switch fabric are looked for, excluding the utopia interfaces. it is important to decide at the beginning what level of fault diagnosis, recovery, and additional functionality is desired. the goal is to be robust to: ? any stuck-at fault, ? any bridging fault within a port, and ? possible card removal. in particular, the system should not be totally disabled by any of the above, although it may operate at a reduced per- formance. in addition, any of the previous failures should be locatable. the system will not necessarily be robust to: figure 33. basic data path (se_d_out/in and se_soc_out/in in forward path, bp_ack_out/in in backward path) qse (switching matrix) a g h qrt-to-qse interface qse-to-qse interface qrt (irt portion) b qrt (ort portion) a a b qrt (irt portion) a b e f e f c d c d qse (switching matrix) e f e f c d c d g h qrt (ort portion) b qse-to-qrt interface forward cell path backward bp/ack path
pmc-sierra, inc. pm73488 qse long form data sheet pmc-980616 issue 3 5 gbit/s atm switch fabric element released datasheet 52 ? all dribbling errors, ? any bridging fault between ports, and ? complex partial failures. as much as possible, the following secondary goals will be taken into account in the algorithms implemented. ? quick and responsive in failure detection, ? localize the problem, and minimize the effect of the problem, ? avoid throughput collapse, ? identify and locate the problem, ? possibly do strong manufacturing test, ? on line diagnostics, and ? automatically detect when a failure resolves itself. 5. 3. fault detection mechanisms several mechanisms are built into the qse and the qrt to facilitate online detection and location of faults within a system. these involve: ? special coding and guaranteed transitions on the bp_ack line. if this is not detected, the condition is flagged, and no data is sent out on the port. ? special coding and guaranteed transitions on the se_soc line. if this is not detected, the port is flagged as failed, and all data from the port is discarded. ? cell present being marked by two bits, nibble 0 is 10xx for cell present or 01xx for cell absent (11xx and 00xx are considered errors, the port is flagged as failed, and all data from the port is discarded). ? idle cell is coded by five nibbles, (01xx, 0000,1000, 0100, 0010, 0001). this pattern verifies no line has a stuck-at or bridging fault. ? closed loop port behavior ensures no data is sent to a bad port. if a port is flagged as failed, then no bp signal is sent back on the bp_ack line. this in turn will be detected by the transmitting qse, and will be flagged. in addition, no data will be sent to that port while the condition exists. ? nibbles 1 through 12 of the cell header are parity protected. for unicast data, in the qrt, a parity errored cell is dropped, but an ack is still issued. in the qse, an onack is issued for parity errored cells. this results in the unicast onacked cell being retransmitted if the parity error did not occur in the last stage. for multicast data, parity errored cells are dropped by both the qrt and qse. ? marked cell count. all input and output ports have a 4-bit cell counter. any cell that goes by with a marked cell count bit set increments this count. (note that unicast traffic has to be acked to increment the count.) modulo 16 arithmetic can be performed on these counts to determine if there was any unexpected cell loss or generation. ? whenever a port is tagged dead due to bp_ack failure, there needs to be two consecutive good instances to make the port alive again. 5. 4. interface behavior in figure 33 on page 51, the various interfaces of interest are labeled a , b , c , d , e , f , g , and h respectively.
pmc-sierra, inc. pm73488 qse long form data sheet pmc-980616 issue 3 5 gbit/s atm switch fabric element released datasheet 53 5. 5. irt-to-switch fabric interface an irt interface consists of a and b in figure 33 on page 51. where a refers to each of the four se_soc_out and se_d_out(3:0) data ports, and b refers to the corresponding bp_ack_in signals in the qrt. the failure conditions detected by the irt on b , and the actions taken are summarized in table 9. 5. 6. qse interface, receive data direction a qse receive interface consists of c and d in figure 33 on page 51. where c refers to each of the four se_soc_in and se_d_in(3:0) data ports, and d refers to the corresponding bp_ack_out signals in the qse. table 9. failure conditions, irt-to switch fabric interface fault detected on b action taken comment cannot lock to special coding and guaranteed transitions on bp_ack_in. idle cells sent out on data interface a . internally to the irt, cells that would have gone out are mnacked, and no multicast cells are generated for the port. bp_ack_fail signaled to the microprocessor. port treated as dead. problem is most likely with the bp_ack_in line. no bp received on bp_ack_in line. idle cells sent out on data interface a . internally to the irt, cells that would have gone out are mnacked, and no multicast cells are generated for the port. bp_remote_fail signaled to the microprocessor. port treated as dead. problem is with the forward data flow, and the qse is signaling this back to the irt. no ack, mnack, or onack received, although unicast cell sent out. cell transmitted treated as sent. ack_live_fail signaled to the microprocessor.
pmc-sierra, inc. pm73488 qse long form data sheet pmc-980616 issue 3 5 gbit/s atm switch fabric element released datasheet 54 the failure conditions detected by the ort on c , and the actions taken are summarized in table 10. 5. 7. qse interface, transmit data direction a qse transmit interface consists of e and f in figure 33 on page 51. where e refers to each of the 32 se_soc_out and se_d_out(3:0) data ports, and f refers to the corresponding bp_ack_in signals in the qse. table 10. failure conditions, qse receive interface fault detected on c action taken comment cannot lock to special coding and guaranteed transitions on se_soc_in. no bp sent out on d . all data discarded. se_input_port_fail signaled to the microprocessor. withholding bp on d signals to the previous stage that the port should not be used. invalid cell present coding on se_d_in(3:0). no bp sent out on d . all data discarded. se_input_port_fail signaled to the microprocessor. most likely due to unconnected input lines that are pulled up or down. withholding bp on d signals to the previous stage that the port should not be used. bad idle cell coding on se_d_in(3:0). no bp sent out on d . all data discarded. se_input_port_fail signaled to the microprocessor. withholding bp on d signals to the previous stage that the port should not be used. parity fail. onack sent out on d for unicast data . multicast data dropped. parity_fail signaled to the microprocessor. qse does not necessarily have time to drop cell by the time it has detected a parity error.
pmc-sierra, inc. pm73488 qse long form data sheet pmc-980616 issue 3 5 gbit/s atm switch fabric element released datasheet 55 the failure conditions detected by the qse on f , and the actions taken are summarized in table 11. 5. 8. switch fabric-to-ort interface an ort interface consists of g and h in figure 33 on page 51. where g refers to each of the four se_soc_in and se_d_in(3:0) data ports, and h refers to the corresponding bp_ack_out signals in the qrt. table 11. failure conditions, qse transmit interface fault detected on f action taken comment cannot lock to special coding and guaranteed transitions on bp_ack_in. idle cells sent out on data interface e . data routed around port if possible. multicast data is dropped if all possible port choices are dead or off. unicast data is optionally dropped if all possible port choices are dead or off. bp_ack_fail signaled to the microprocessor. port treated as dead. problem is most likely with the bp_ack line. no bp received on bp_ack_in line. idle cells sent out on data interface e . data routed around port if possible. multicast data is dropped if all possible port choices are dead or off. unicast data is optionally dropped if all possible port choices are dead or off. bp_remote_fail signaled to the microprocessor. port treated as dead. problem is with the forward data flow. no ack, mnack, or onack received on bp_ack_in line. no action taken. this contingency is not monitored in the qse.
pmc-sierra, inc. pm73488 qse long form data sheet pmc-980616 issue 3 5 gbit/s atm switch fabric element released datasheet 56 the failure conditions detected by the ort on g , and the actions taken are summarized in table 12. 5. 9. types of failures and their manifestation possible faults, the effects and how they affect the network are shown in table 13. table 12. failure conditions, switch fabric-to-ort interface fault detected on g action taken comment cannot lock to special coding and guaranteed transitions on se_soc_in. no bp sent out on h . all data discarded. se_input_port_fail signaled to the microprocessor. withholding bp on h signals to the previous stage that the port should not be used. invalid cell present coding on se_d_in(3:0). no bp sent out on h . all data discarded. se_input_port_fail signaled to the microprocessor. most likely due to unconnected input lines that are pulled up or down. withholding bp on h signals to the previous stage that the port should not be used. bad idle cell coding on se_d_in(3:0). no bp sent out on h . all data discarded. se_input_port_fail signaled to the microprocessor. withholding bp on h signals to the previous stage that the port should not be used. parity fail. ack sent out on h . parity errored cell dropped. tx_parity_fail signaled to the microprocessor. ack already sent by the time the qrt has detected a parity error. note that in this case we have acked a cell that was dropped. table 13. faults fault manifestation effect on network wire connection data line from se_d(3:0) stuck at 0 or 1. invalid idle cell, with some 10/01 fail and parity error. port shut down on receipt of first bad idle cell until condition is fixed, as port failure is sent back to source of data by the lack of bp indication. se_soc line stuck at 0 or 1. loss of lock on special coding on se_soc_in. port shut down until condition is fixed, as port failure is sent back to source of data by the lack of bp indication. bp_ack line stuck at 0 or 1. loss of lock on special coding on bp_ack_in. port shut down until the condition is fixed. bridging fault within a port. invalid idle cell, with some 10/01 fail and parity error. port shut down on receipt of first bad idle cell until condition is fixed, as port failure is sent back to source of data by the lack of bp indication. qrt and qse port failures no se_soc_out generation. loss of lock on special coding on se_soc_in. port shut down until condition is fixed, as port failure is sent back to source of data by the lack of bp indication.
pmc-sierra, inc. pm73488 qse long form data sheet pmc-980616 issue 3 5 gbit/s atm switch fabric element released datasheet 57 no/invalid data generated. 10/01 fail, or parity error, invalid idle cell. port shut down on receipt of first bad idle cell until condition is fixed, as port failure is sent back to source of data by the lack of bp indication. no bp_ack_out generation. loss of lock on special coding on bp_ack_in. port shut down until the condition is fixed. qse chip failures multicast handling. cell loss or generation. detection possible using marked cell count. mc cell pool buffer. parity error in header or cell. only detection in header, not in payload. partial cell buffers. parity error in header and cell. parity error. multicast and unicast selection networks. cell gets out on wrong port, cell duplicated, cell lost. cell to wrong port may be noticed by receiving qrt, if that vc is not active. cell duplication and cell loss detection possible using marked cell count. arbiter. cell lost. detection possible using marked cell count. table 13. faults fault manifestation effect on network
pmc-sierra, inc. pm73488 qse long form data sheet pmc-980616 issue 3 5 gbit/s atm switch fabric element released datasheet 58 6 signal descriptions 6.1 package diagram a 596-pin enhanced plastic ball grid array (epbga), shown in figure 34 (part 1 and part 2), is used for the qse.the package measurements are shown in millimeters. figure 34. 596-ball enhanced plastic bga physical dimensions diagram (top view) 0.86 0.15 0.25 0.10 // c c 0.60 0.1 2.98 max. 1.14 0.125 measurements are shown in millimeters. not drawn to scale. notes: 1. l2a0962 is the lsi part number. 2. l_____b is the wafer batch code. 3. lyyww is the assembly date code. 4. dimensions are for reference. 5. controlling dimension: millimeter. 6. // = parallelism tolerance. 40.00 0.20 40.00 0.20 PM73488-PI l2a0962 l_______b 30.00 max. 30.00 max. lyyww qse
pmc-sierra, inc. pm73488 qse long form data sheet pmc-980616 issue 3 5 gbit/s atm switch fabric element released datasheet 59 figure 35. 596-ball enhanced plastic bga physical dimensions diagram (bottom view) notes: 1. controlling dimension: millimeter. 2. pcb material: high temperature glass/epoxy resin cloth (that is, driclad, mcl-679, or equivalent). solder resist: photoimagable (that is, vacrel 8130, dsr3241, psr4000, or equivalent). 3. if you need a measurement not shown in this figure, contact pmc. 0.75 0.15 1.27 1 2 4 3 5 6 8 7 9 10 12 11 13 14 16 15 17 18 20 19 21 22 24 23 25 26 28 27 29 30 a b c d e f g h j k l m n p r t u v w y aa ab ac ad ae af ag ah aj ak 9 36.83 40.00 0.20 36.83 40.00 0.20 1.27 c c a b s s measurements are shown in millimeters. not drawn to scale. 0.30 0.10 s s
pmc-sierra, inc. pm73488 qse long form data sheet pmc-980616 issue 3 5 gbit/s atm switch fabric element released datasheet 60 6.2 signal locations (signal name to ball) table 14. signal locations (signal name to ball) signal name ball signal name ball signal name ball signal name ball bp_ack_in(0) l29 se_d_in11(1) b7 se_d_out16(2) ae24 gnd r3 bp_ack_in(1) k30 se_d_in11(2) c9 se_d_out16(3) ag26 gnd t3 bp_ack_in(2) g30 se_d_in11(3) d10 se_d_out17(0) aj28 gnd v1 bp_ack_in(3) n27 se_d_in12(0) a4 se_d_out17(1) ae22 gnd aa2 bp_ack_in(4) j29 se_d_in12(1) c8 se_d_out17(2) ah27 gnd w4 bp_ack_in(5) m28 se_d_in12(2) d9 se_d_out17(3) af23 gnd af1 bp_ack_in(6) h30 se_d_in12(3) a3 se_d_out18(0) ak28 gnd ad3 bp_ack_in(7) l27 se_d_in13(0) b5 se_d_out18(1) ah25 gnd aj2 bp_ack_in(8) m26 se_d_in13(1) f10 se_d_out18(2) aj26 gnd ag4 bp_ack_in(9) h29 se_d_in13(2) b4 se_d_out18(3) ae21 gnd ae6 bp_ack_in(10) k28 se_d_in13(3) f9 se_d_out19(0) af21 gnd af3 bp_ack_in(11) f30 se_d_in14(0) e8 se_d_out19(1) af22 gnd ah5 bp_ack_in(12) n25 se_d_in14(1) b3 se_d_out19(2) ah23 gnd ak5 bp_ack_in(13) m25 se_d_in14(2) d7 se_d_out19(3) aj27 gnd ah7 bp_ack_in(14) j28 se_d_in14(3) f7 se_d_out20(0) af20 gnd aj10 bp_ack_in(15) l26 se_d_in15(0) d6 se_d_out20(1) ak27 gnd ag12 bp_ack_in(16) d30 se_d_in15(1) e7 se_d_out20(2) aj24 gnd ak13 bp_ack_in(17) g29 se_d_in15(2) e6 se_d_out20(3) ag22 gnd ah15 bp_ack_in(18) j27 se_d_in15(3) d5 se_d_out21(0) ak25 gnd ah16 bp_ack_in(19) k27 se_d_in16(0) f3 se_d_out21(1) ae18 gnd ak18 bp_ack_in(20) k26 se_d_in16(1) c1 se_d_out21(2) ae19 gnd aj21 bp_ack_in(21) j26 se_d_in16(2) d2 se_d_out21(3) ah22 gnd ag19 bp_ack_in(22) h28 se_d_in16(3) h3 se_d_out22(0) ag20 gnd ak26 bp_ack_in(23) d29 se_d_in17(0) k5 se_d_out22(1) af19 gnd ah24 bp_ack_in(24) c30 se_d_in17(1) k4 se_d_out22(2) aj23 gnd ah26 bp_ack_in(25) f28 se_d_in17(2) j4 se_d_out22(3) ah21 gnd aj29 bp_ack_in(26) e29 se_d_in17(3) g2 se_d_out23(0) ag18 gnd ag27 bp_ack_in(27) k25 se_d_in18(0) l5 se_d_out23(1) aj22 gnd ae25 bp_ack_in(28) c29 se_d_in18(1) j3 se_d_out23(2) ah19 gnd af28 bp_ack_in(29) j25 se_d_in18(2) m6 se_d_out23(3) ak23 gnd af30 bp_ack_in(30) d28 se_d_in18(3) n6 se_d_out24(0) ae17 gnd ad28 bp_ack_in(31) h26 se_d_in19(0) k3 se_d_out24(1) ah18 gnd aa29 bp_ack_out(0) ab5 se_d_in19(1) h2 se_d_out24(2) aj20 gnd w27 bp_ack_out(1) af2 se_d_in19(2) m5 se_d_out24(3) ak21 gnd v30 bp_ack_out(2) aa6 se_d_in19(3) l4 se_d_out25(0) ak20 gnd t28
pmc-sierra, inc. pm73488 qse long form data sheet pmc-980616 issue 3 5 gbit/s atm switch fabric element released datasheet 61 bp_ack_out(3) ag2 se_d_in20(0) m3 se_d_out25(1) aj19 gnd r28 bp_ack_out(4) ab6 se_d_in20(1) j2 se_d_out25(2) ae16 gnd n30 bp_ack_out(5) ae3 se_d_in20(2) n4 se_d_out25(3) af18 gnd k29 bp_ack_out(6) ac5 se_d_in20(3) g1 se_d_out26(0) ag17 gnd m27 bp_ack_out(7) ah2 se_d_in21(0) l2 se_d_out26(1) af16 gnd e30 bp_ack_out(8) ad4 se_d_in21(1) n3 se_d_out26(2) aj18 gnd g28 bp_ack_out(9) ad6 se_d_in21(2) p6 se_d_out26(3) af17 gnd e28 bp_ack_out(10) ag3 se_d_in21(3) n5 se_d_out27(0) ak19 gnd b29 bp_ack_out(11) ae4 se_d_in22(0) m2 se_d_out27(1) ak17 gnd d27 bp_ack_out(12) ad5 se_d_in22(1) l1 se_d_out27(2) ah17 gnd f25 bp_ack_out(13) ae5 se_d_in22(2) p5 se_d_out27(3) ag16 gnd c26 bp_ack_out(14) af4 se_d_in22(3) n2 se_d_out28(0) ag15 gnd a26 bp_ack_out(15) aj1 se_d_in23(0) p4 se_d_out28(1)) ak15 gnd c24 bp_ack_out(16) ak2 se_d_in23(1) r4 se_d_out28(2) ak14 gnd b21 bp_ack_out(17) ag5 se_d_in23(2) p3 se_d_out28(3) ak16 gnd d19 bp_ack_out(18) af6 se_d_in23(3) p1 se_d_out29(0) ah14 gnd a18 bp_ack_out(19) af7 se_d_in24(0) r2 se_d_out29(1) aj13 gnd c16 bp_ack_out(20) ag6 se_d_in24(1) t2 se_d_out29(2) af15 gnd c15 bp_ack_out(21) ah4 se_d_in24(2) r1 se_d_out29(3) ak12 gnd a13 bp_ack_out(22) ae7 se_d_in24(3) u1 se_d_out30(0) af14 gnd b10 bp_ack_out(23) ag7 se_d_in25(0) t4 se_d_out30(1) ae15 gnd d12 bp_ack_out(24) aj3 se_d_in25(1) w1 se_d_out30(2) ag14 gnd a5 bp_ack_out(25) af8 se_d_in25(2) t5 se_d_out30(3) ak11 gnd c7 bp_ack_out(26) ah6 se_d_in25(3) v2 se_d_out31(0) ak10 gnd c5 bp_ack_out(27) ae9 se_d_in26(0) y1 se_d_out31(1) aj12 gnd y20 bp_ack_out(28) aj4 se_d_in26(1) u4 se_d_out31(2) ah13 gnd w19 bp_ack_out(29) ae10 se_d_in26(2) t6 se_d_out31(3) ae14 gnd u19 bp_ack_out(30) aj5 se_d_in26(3) u5 /oe d3 gnd p19 bp_ack_out(31) af9 se_d_in27(0) v3 reset af13 gnd m19 cell_24_start c2 se_d_in27(1) w2 se_soc_in(0) b22 gnd l20 cell_start j6 se_d_in27(2) aa1 se_soc_in(1) c18 gnd w17 ram_add(17) ah1 se_d_in27(3) v5 se_soc_in(2) a20 gnd u17 ram_add(18) af12 se_d_in28(0) y2 se_soc_in(3) d16 gnd p17 /iddtn g5 se_d_in28(1) w3 se_soc_in(4) b15 gnd m17 stat_out k6 se_d_in28(2) ac1 se_soc_in(5) a12 gnd w14 ctrl_in e2 se_d_in28(3) ad1 se_soc_in(6) d14 gnd u14 table 14. signal locations (signal name to ball) (continued) signal name ball signal name ball signal name ball signal name ball
pmc-sierra, inc. pm73488 qse long form data sheet pmc-980616 issue 3 5 gbit/s atm switch fabric element released datasheet 62 /ack aj11 se_d_in29(0) ab2 se_soc_in(7) b12 gnd p14 add(0) ak3 se_d_in29(1) aa3 se_soc_in(8) c12 gnd m14 add(1) ag9 se_d_in29(2) y4 se_soc_in(9) c10 gnd y11 add(2) ah8 se_d_in29(3) v6 se_soc_in(10) e11 gnd w12 add(3) ak4 se_d_in30(0) ac2 se_soc_in(11) e10 gnd u12 add(4) af10 se_d_in30(1) y5 se_soc_in(12) e9 gnd p12 add(5) ag10 se_d_in30(2) ae1 se_soc_in(13) c6 gnd m12 add(6) ah9 se_d_in30(3) ad2 se_soc_in(14) c4 gnd l11 add(7) aj7 se_d_in31(0) aa4 se_soc_in(15) a2 gnd w21 /cs ak7 se_d_in31(1) aa5 se_soc_in(16) j5 gnd aa12 data(0) ak6 se_d_in31(2) ag1 se_soc_in(17) d1 gnd m10 data(1) af11 se_d_in31(3) ac3 se_soc_in(18) f1 gnd k19 data(2) aj8 se_d_out00(0) p26 se_soc_in(19) h1 gnd p10 data(3) ae12 se_d_out00(1) l30 se_soc_in(20) k1 gnd u10 data(4) ae13 se_d_out00(2) m29 se_soc_in(21) r6 gnd w10 data(5) ag11 se_d_out00(3) r25 se_soc_in(22) r5 gnd k12 data(6) ah10 se_d_out01(0) r27 se_soc_in(23) m1 gnd k14 data(7) aj9 se_d_out01(1) p27 se_soc_in(24) t1 gnd aa14 /intr ag13 se_d_out01(2) r26 se_soc_in(25) u3 gnd k17 /rd ak8 se_d_out01(3) n29 se_soc_in(26) u6 gnd aa17 /wr ah12 se_d_out02(0) r29 se_soc_in(27) v4 gnd aa19 /pll_bypass p25 se_d_out02(1) m30 se_soc_in(28) w5 gnd m21 pll_vdd aj30 se_d_out02(2) p30 se_soc_in(29) w6 gnd p21 pll_vss af27 se_d_out02(3) p28 se_soc_in(30) ab3 gnd u21 not used h5 se_d_out03(0) t30 se_soc_in(31) ab4 v dd a1 /scan_en g6 se_d_out03(1) u30 se_soc_out0 n26 v dd c3 /scan_trst e4 se_d_out03(2) r30 se_soc_out1 t27 v dd e5 scan_tck g4 se_d_out03(3) t29 se_soc_out2 ac30 v dd f2 scan_tdi b1 se_d_out04(0) u28 se_soc_out3 ab27 v dd h4 scan_tdo f5 se_d_out04(1) v29 se_soc_out4 ag25 v dd j1 scan_tms f4 se_d_out04(2) t26 se_soc_out5 ag21 v dd l3 se_clk_bypass af25 se_d_out04(3) w30 se_soc_out6 ak24 v dd p2 se_clk aj16 se_d_out05(0) u26 se_soc_out7 aj15 v dd u2 se_d_in00(0) e19 se_d_out05(1) t25 ram_add(0) g26 v dd ab1 se_d_in00(1) d20 se_d_out05(2) u27 ram_add(1) g27 v dd y3 se_d_in00(2) a23 se_d_out05(3) y30 ram_add(2) g25 v dd ae2 table 14. signal locations (signal name to ball) (continued) signal name ball signal name ball signal name ball signal name ball
pmc-sierra, inc. pm73488 qse long form data sheet pmc-980616 issue 3 5 gbit/s atm switch fabric element released datasheet 63 se_d_in00(3) c19 se_d_out06(0) aa30 ram_add(3) e27 v dd ac4 se_d_in01(0) d18 se_d_out06(1) w29 ram_add(4) f27 v dd ak1 se_d_in01(1) a24 se_d_out06(2) v28 ram_add(5) f26 v dd ah3 se_d_in01(2) a21 se_d_out06(3) u25 ram_add(6) b30 v dd af5 se_d_in01(3) b20 se_d_out07(0) w28 ram_add(7) a29 v dd aj6 se_d_in02(0) f17 se_d_out07(1) y29 ram_add(8) e25 v dd ag8 se_d_in02(1) e18 se_d_out07(2) v27 ram_add(9) d25 v dd ak9 se_d_in02(2) f16 se_d_out07(3) v26 ram_add(10) d26 v dd ah11 se_d_in02(3) b19 se_d_out08(0) aa28 ram_add(11) f24 v dd aj14 se_d_in03(0) e17 se_d_out08(1) ab29 ram_add(12) d24 v dd aj17 se_d_in03(1) b18 se_d_out08(2) w26 ram_add(13) e24 v dd ak22 se_d_in03(2) e16 se_d_out08(3) ad30 ram_add(14) e23 v dd ah20 se_d_in03(3) d17 se_d_out09(0) ac29 ram_add(15) c27 v dd aj25 se_d_in04(0) c17 se_d_out09(1) w25 ram_clk b23 v dd ag23 se_d_in04(1) a17 se_d_out09(2) v25 ram_data(0) f22 v dd ak30 se_d_in04(2) a19 se_d_out09(3) y27 ram_data(1) b28 v dd ah28 se_d_in04(3) b16 se_d_out10(0) ab28 ram_data(2) f21 v dd af26 se_d_in05(0) a16 se_d_out10(1) ad29 ram_data(3) b26 v dd ae29 se_d_in05(1) a14 se_d_out10(2) ae30 ram_data(4) c25 v dd ac27 se_d_in05(2) a15 se_d_out10(3) y26 ram_data(5) a28 v dd ab30 se_d_in05(3) d15 se_d_out11(0) ac28 ram_data(6) b27 v dd y28 se_d_in06(0) e15 se_d_out11(1) ag30 ram_data(7) c23 v dd u29 se_d_in06(1) b13 se_d_out11(2) aa26 ram_data(8) e22 v dd p29 se_d_in06(2) c14 se_d_out11(3) aa27 ram_data(9) e21 v dd j30 se_d_in06(3) a11 se_d_out12(0) aa25 ram_data(10) d21 v dd l28 se_d_in07(0) f15 se_d_out12(1) af29 ram_data(11) d22 v dd f29 se_d_in07(1) e14 se_d_out12(2) ab26 ram_data(12) b24 v dd h27 se_d_in07(2) f14 se_d_out12(3) ah30 ram_data(13) a27 v dd a30 se_d_in07(3) c13 se_d_out13(0) ac26 ram_data(14) e20 v dd c28 se_d_in08(0) a10 se_d_out13(1) ae28 ram_data(15) c22 v dd e26 se_d_in08(1) e13 se_d_out13(2) ab25 /ram_oe c21 v dd b25 se_d_in08(2) d13 se_d_out13(3) ag29 /ram_wr a25 v dd d23 se_d_in08(3) b11 se_d_out14(0) ag28 /test_mode n28 v dd a22 se_d_in09(0) a8 se_d_out14(1) ad25 gnd b2 v dd c20 se_d_in09(1) a7 se_d_out14(2) ad27 gnd d4 v dd b17 se_d_in09(2) e12 se_d_out14(3) ah29 gnd f6 v dd b14 table 14. signal locations (signal name to ball) (continued) signal name ball signal name ball signal name ball signal name ball
pmc-sierra, inc. pm73488 qse long form data sheet pmc-980616 issue 3 5 gbit/s atm switch fabric element released datasheet 64 se_d_in09(3) b9 se_d_out15(0) ak29 gnd e3 v dd a9 se_d_in10(0) d11 se_d_out15(1) ae26 gnd e1 v dd c11 se_d_in10(1) f13 se_d_out15(2) ad26 gnd g3 v dd b6 se_d_in10(2) f12 se_d_out15(3) ae27 gnd k2 v dd d8 se_d_in10(3) b8 se_d_out16(0) af24 gnd m4 ram_add(16) f19 se_d_in11(0) a6 se_d_out16(1) ag24 gnd n1 ram_parity f18 table 14. signal locations (signal name to ball) (continued) signal name ball signal name ball signal name ball signal name ball
pmc-sierra, inc. pm73488 qse long form data sheet pmc-980616 issue 3 5 gbit/s atm switch fabric element released datasheet 65 6.3 signal locations (ball to signal name) table 15. signal locations (ball to signal name) ball signal name ball signal name ball signal name) all signal name a1 v dd f1 se_soc_in18 t3 gnd af5 v dd a2 se_soc_in15 f2 v dd t4 se_d_in25(0) af6 bp_ack_out(18) a3 se_d_in12(3) f3 se_d_in16(0) t5 se_d_in25(2) af7 bp_ack_out(19) a4 se_d_in12(0) f4 scan_tms t6 se_d_in26(2) af8 bp_ack_out(25) a5 gnd f5 scan_tdo t25 se_d_out05(1) af9 bp_ack_out(31) a6 se_d_in11(0) f6 gnd t26 se_d_out04(2) af10 add(4) a7 se_d_in09(1) f7 se_d_in14(3) t27 se_soc_out1 af11 data(1) a8 se_d_in09(0) f9 se_d_in13(3) t28 gnd af12 ram_add(18) a9 v dd f10 se_d_in13(1) t29 se_d_out03(3) af13 reset a10 se_d_in08(0) f12 se_d_in10(2) t30 se_d_out03(0) af14 se_d_out30(0) a11 se_d_in06(3) f13 se_d_in10(1) u1 se_d_in24(3) af15 se_d_out29(2) a12 se_soc_in05 f14 se_d_in07(2) u2 v dd af16 se_d_out26(1) a13 gnd f15 se_d_in07(0) u3 se_soc_in25 af17 se_d_out26(3) a14 se_d_in05(1) f16 se_d_in02(2) u4 se_d_in26(1) af18 se_d_out25(3) a15 se_d_in05(2) f17 se_d_in02(0) u5 se_d_in26(3) af19 se_d_out22(1) a16 se_d_in05(0) f18 ram_parity u6 se_soc_in26 af20 se_d_out20(0) a17 se_d_in04(1) f19 ram_add(16) u10 gnd af21 se_d_out19(0) a18 gnd f21 ram_data(2) u12 gnd af22 se_d_out19(1) a19 se_d_in04(2) f22 ram_data(0) u14 gnd af23 se_d_out17(3) a20 se_soc_in02 f24 ram_add(11) u17 gnd af24 se_d_out16(0) a21 se_d_in01(2) f25 gnd u19 gnd af25 se_clk_bypass a22 v dd f26 ram_add(5) u21 gnd af26 v dd a23 se_d_in00(2) f27 ram_add(4) u25 se_d_out06(3) af27 pll_vss a24 se_d_in01(1) f28 bp_ack_in(25) u26 se_d_out05(0) af28 gnd a25 /ram_wr f29 v dd u27 se_d_out05(2) af29 se_d_out12(1) a26 gnd f30 bp_ack_in(11) u28 se_d_out04(0) af30 gnd a27 ram_data(13) g1 se_d_in20(3) u29 v dd ag1 se_d_in31(2) a28 ram_data(5) g2 se_d_in17(3) u30 se_d_out03(1) ag2 bp_ack_out(3) a29 ram_add(7) g3 gnd v1 gnd ag3 bp_ack_out(10) a30 v dd g4 scan_tck v2 se_d_in25(3) ag4 gnd b1 scan_tdi g5 /iddtn v3 se_d_in27(0) ag5 bp_ack_out(17) b2 gnd g6 /scan_en v4 se_soc_in27 ag6 bp_ack_out(20) b3 se_d_in14(1) g25 ram_add(2) v5 se_d_in27(3) ag7 bp_ack_out(23) b4 se_d_in13(2) g26 ram_add(0) v6 se_d_in29(3) ag8 v dd b5 se_d_in13(0) g27 ram_add(1) v25 se_d_out09(2) ag9 add(1)
pmc-sierra, inc. pm73488 qse long form data sheet pmc-980616 issue 3 5 gbit/s atm switch fabric element released datasheet 66 b6 v dd g28 gnd v26 se_d_out07(3) ag10 add(5) b7 se_d_in11(1) g29 bp_ack_in(17) v27 se_d_out07(2) ag11 data(5) b8 se_d_in10(3) g30 bp_ack_in(2) v28 se_d_out06(2) ag12 gnd b9 se_d_in09(3) h1 se_soc_in19 v29 se_d_out04(1) ag13 /intr b10 gnd h2 se_d_in19(1) v30 gnd ag14 se_d_out30(2) b11 se_d_in08(3) h3 se_d_in16(3) w1 se_d_in25(1) ag15 se_d_out28(0) b12 se_soc_in07 h4 v dd w2 se_d_in27(1) ag16 se_d_out27(3) b13 se_d_in06(1) h5 not used w3 se_d_in28(1) ag17 se_d_out26(0) b14 v dd h26 bp_ack_in(31) w4 gnd ag18 se_d_out23(0) b15 se_soc_in04 h27 v dd w5 se_soc_in28 ag19 gnd b16 se_d_in04(3) h28 bp_ack_in(22) w6 se_soc_in29 ag20 se_d_out22(0) b17 v dd h29 bp_ack_in(9) w10 gnd ag21 se_soc_out5 b18 se_d_in03(1) h30 bp_ack_in(6) w12 gnd ag22 se_d_out20(3) b19 se_d_in02(3) j1 v dd w14 gnd ag23 v dd b20 se_d_in01(3) j2 se_d_in20(1) w17 gnd ag24 se_d_out16(1) b21 gnd j3 se_d_in18(1) w19 gnd ag25 se_soc_out4 b22 se_soc_in00 j4 se_d_in17(2) w21 gnd ag26 se_d_out16(3) b23 ram_clk j5 se_soc_in16 w25 se_d_out09(1) ag27 gnd b24 ram_data(12) j6 cell_start w26 se_d_out08(2) ag28 se_d_out14(0) b25 v dd j25 bp_ack_in(29) w27 gnd ag29 se_d_out13(3) b26 ram_data(3) j26 bp_ack_in(21) w28 se_d_out07(0) ag30 se_d_out11(1) b27 ram_data(6) j27 bp_ack_in(18) w29 se_d_out06(1) ah1 ram_add(17) b28 ram_data(1) j28 bp_ack_in(14) w30 se_d_out04(3) ah2 bp_ack_out(7) b29 gnd j29 bp_ack_in(4) y1 se_d_in26(0) ah3 v dd b30 ram_add(6) j30 v dd y2 se_d_in28(0) ah4 bp_ack_out(21) c1 se_d_in16(1) k1 se_soc_in20 y3 v dd ah5 gnd c2 cell_24_start k2 gnd y4 se_d_in29(2) ah6 bp_ack_out(26) c3 v dd k3 se_d_in19(0) y5 se_d_in30(1) ah7 gnd c4 se_soc_in14 k4 se_d_in17(1) y11 gnd ah8 add(2) c5 gnd k5 se_d_in17(0) y20 gnd ah9 add(6) c6 se_soc_in13 k6 stat_out y26 se_d_out10(3) ah10 data(6) c7 gnd k12 gnd y27 se_d_out09(3) ah11 v dd c8 se_d_in12(1) k14 gnd y28 v dd ah12 /wr c9 se_d_in11(2) k17 gnd y29 se_d_out07(1) ah13 se_d_out31(2) c10 se_soc_in09 k19 gnd y30 se_d_out05(3) ah14 se_d_out29(0) c11 v dd k25 bp_ack_in(27) aa1 se_d_in27(2) ah15 gnd table 15. signal locations (ball to signal name) (continued) ball signal name ball signal name ball signal name) all signal name
pmc-sierra, inc. pm73488 qse long form data sheet pmc-980616 issue 3 5 gbit/s atm switch fabric element released datasheet 67 c12 se_soc_in08 k26 bp_ack_in(20) aa2 gnd ah16 gnd c13 se_d_in07(3) k27 bp_ack_in(19) aa3 se_d_in29(1) ah17 se_d_out27(2) c14 se_d_in06(2) k28 bp_ack_in(10) aa4 se_d_in31(0) ah18 se_d_out24(1) c15 gnd k29 gnd aa5 se_d_in31(1) ah19 se_d_out23(2) c16 gnd k30 bp_ack_in(1) aa6 bp_ack_out(2) ah20 v dd c17 se_d_in04(0) l1 se_d_in22(1) aa12 gnd ah21 se_d_out22(3) c18 se_soc_in01 l2 se_d_in21(0) aa14 gnd ah22 se_d_out21(3) c19 se_d_in00(3) l3 v dd aa17 gnd ah23 se_d_out19(2) c20 v dd l4 se_d_in19(3) aa19 gnd ah24 gnd c21 /ram_oe l5 se_d_in18(0) aa25 se_d_out12(0) ah25 se_d_out18(1) c22 ram_data(15) l11 gnd aa26 se_d_out11(2) ah26 gnd c23 ram_data(7) l20 gnd aa27 se_d_out11(3) ah27 se_d_out17(2) c24 gnd l26 bp_ack_in(15) aa28 se_d_out08(0) ah28 v dd c25 ram_data(4) l27 bp_ack_in(7) aa29 gnd ah29 se_d_out14(3) c26 gnd l28 v dd aa30 se_d_out06(0) ah30 se_d_out12(3) c27 ram_add(15) l29 bp_ack_in(0) ab1 v dd aj1 bp_ack_out(15) c28 v dd l30 se_d_out00(1) ab2 se_d_in29(0) aj2 gnd c29 bp_ack_in(28) m1 se_soc_in23 ab3 se_soc_in30 aj3 bp_ack_out(24) c30 bp_ack_in(24) m2 se_d_in22(0) ab4 se_soc_in31 aj4 bp_ack_out(28) d1 se_soc_in17 m3 se_d_in20(0) ab5 bp_ack_out(0) aj5 bp_ack_out(30) d2 se_d_in16(2) m4 gnd ab6 bp_ack_out(4) aj6 v dd d3 /oe m5 se_d_in19(2) ab25 se_d_out13(2) aj7 add(7) d4 gnd m6 se_d_in18(2) ab26 se_d_out12(2) aj8 data(2) d5 se_d_in15(3) m10 gnd ab27 se_soc_out3 aj9 data(7) d6 se_d_in15(0) m12 gnd ab28 se_d_out10(0) aj10 gnd d7 se_d_in14(2) m14 gnd ab29 se_d_out08(1) aj11 /ack d8 v dd m17 gnd ab30 v dd aj12 se_d_out31(1) d9 se_d_in12(2) m19 gnd ac1 se_d_in28(2) aj13 se_d_out29(1) d10 se_d_in11(3) m21 gnd ac2 se_d_in30(0) aj14 v dd d11 se_d_in10(0) m25 bp_ack_in(13) ac3 se_d_in31(3) aj15 se_soc_out7 d12 gnd m26 bp_ack_in(8) ac4 v dd aj16 se_clk d13 se_d_in08(2) m27 gnd ac5 bp_ack_out(6) aj17 v dd d14 se_soc_in06 m28 bp_ack_in(5) ac26 se_d_out13(0) aj18 se_d_out26(2) d15 se_d_in05(3) m29 se_d_out00(2) ac27 v dd aj19 se_d_out25(1) d16 se_soc_in03 m30 se_d_out02(1) ac28 se_d_out11(0) aj20 se_d_out24(2) d17 se_d_in03(3) n1 gnd ac29 se_d_out09(0) aj21 gnd table 15. signal locations (ball to signal name) (continued) ball signal name ball signal name ball signal name) all signal name
pmc-sierra, inc. pm73488 qse long form data sheet pmc-980616 issue 3 5 gbit/s atm switch fabric element released datasheet 68 d18 se_d_in01(0) n2 se_d_in22(3) ac30 se_soc_out2 aj22 se_d_out23(1) d19 gnd n3 se_d_in21(1) ad1 se_d_in28(3) aj23 se_d_out22(2) d20 se_d_in00(1) n4 se_d_in20(2) ad2 se_d_in30(3) aj24 se_d_out20(2) d21 ram_data(10) n5 se_d_in21(3) ad3 gnd aj25 v dd d22 ram_data(11) n6 se_d_in18(3) ad4 bp_ack_out(8) aj26 se_d_out18(2) d23 v dd n25 bp_ack_in(12) ad5 bp_ack_out(12) aj27 se_d_out19(3) d24 ram_add(12) n26 se_soc_out0 ad6 bp_ack_out(9) aj28 se_d_out17(0) d25 ram_add(9) n27 bp_ack_in(3) ad25 se_d_out14(1) aj29 gnd d26 ram_add(10) n28 /test_mode ad26 se_d_out15(2) aj30 pll_vdd d27 gnd n29 se_d_out01(3) ad27 se_d_out14(2) ak1 v dd d28 bp_ack_in(30) n30 gnd ad28 gnd ak2 bp_ack_out(16) d29 bp_ack_in(23) p1 se_d_in23(3) ad29 se_d_out10(1) ak3 add(0) d30 bp_ack_in(16) p2 v dd ad30 se_d_out08(3) ak4 add(3) e1 gnd p3 se_d_in23(2) ae1 se_d_in30(2) ak5 gnd e2 ctrl_in p4 se_d_in23(0) ae2 v dd ak6 data(0) e3 gnd p5 se_d_in22(2) ae3 bp_ack_out(5) ak7 /cs e4 /scan_trst p6 se_d_in21(2) ae4 bp_ack_out(11) ak8 /rd e5 v dd p10 gnd ae5 bp_ack_out(13) ak9 v dd e6 se_d_in15(2) p12 gnd ae6 gnd ak10 se_d_out31(0) e7 se_d_in15(1) p14 gnd ae7 bp_ack_out(22) ak11 se_d_out30(3) e8 se_d_in14(0) p17 gnd ae9 bp_ack_out(27) ak12 se_d_out29(3) e9 se_soc_in12 p19 gnd ae10 bp_ack_out(29) ak13 gnd e10 se_soc_in11 p21 gnd ae12 data(3) ak14 se_d_out28(2) e11 se_soc_in10 p25 /pll_bypass ae13 data(4) ak15 se_d_out28(1) e12 se_d_in09(2) p26 se_d_out00(0) ae14 se_d_out31(3) ak16 se_d_out28(3) e13 se_d_in08(1) p27 se_d_out01(1) ae15 se_d_out30(1) ak17 se_d_out27(1) e14 se_d_in07(1) p28 se_d_out02(3) ae16 se_d_out25(2) ak18 gnd e15 se_d_in06(0) p29 v dd ae17 se_d_out24(0) ak19 se_d_out27(0) e16 se_d_in03(2) p30 se_d_out02(2) ae18 se_d_out21(1) ak20 se_d_out25(0) e17 se_d_in03(0) r1 se_d_in24(2) ae19 se_d_out21(2) ak21 se_d_out24(3) e18 se_d_in02(1) r2 se_d_in24(0) ae21 se_d_out18(3) ak22 v dd e19 se_d_in00(0) r3 gnd ae22 se_d_out17(1) ak23 se_d_out23(3) e20 ram_data(14) r4 se_d_in23(1) ae24 se_d_out16(2) ak24 se_soc_out6 e21 ram_data(9) r5 se_soc_in22 ae25 gnd ak25 se_d_out21(0) e22 ram_data(8) r6 se_soc_in21 ae26 se_d_out15(1) ak26 gnd e23 ram_add(14) r25 se_d_out00(3) ae27 se_d_out15(3) ak27 se_d_out20(1) table 15. signal locations (ball to signal name) (continued) ball signal name ball signal name ball signal name) all signal name
pmc-sierra, inc. pm73488 qse long form data sheet pmc-980616 issue 3 5 gbit/s atm switch fabric element released datasheet 69 e24 ram_add(13) r26 se_d_out01(2) ae28 se_d_out13(1) ak28 se_d_out18(0) e25 ram_add(8) r27 se_d_out01(0) ae29 v dd ak29 se_d_out15(0) e26 v dd r28 gnd ae30 se_d_out10(2) ak30 v dd e27 ram_add(3) r29 se_d_out02(0) af1 gnd e28 gnd r30 se_d_out03(2) af2 bp_ack_out(1) e29 bp_ack_in(26) t1 se_soc_in24 af3 gnd e30 gnd t2 se_d_in24(1) af4 bp_ack_out(14) table 15. signal locations (ball to signal name) (continued) ball signal name ball signal name ball signal name) all signal name
pmc-sierra, inc. pm73488 qse long form data sheet pmc-980616 issue 3 5 gbit/s atm switch fabric element released datasheet 70 6.4 pin descriptions all inputs except se_clk are 5v tolerant. all bidirectional signals are 5 v tolerant. other outputs are not 5 v toler- ant. all pins have pull-ups except /iddtn. all inputs have schmitt triggers, except the scan_tdi, scan_tms, /scan_trst, /scan_en, /test_mode, /pll_bypass, data[7:0] (which is a bi-di) and ram_data[15:0] (which is also a bi-di). for outputs, the drive strength listed in the type column (in table 16 on page 72 through table 20 on page 81 ) is in milliamperes. (for example, out 5 is and output with a drive strength of 5ma.) all switch fabric interface outputs, namely se_soc_out, se_d_out and bp_ack_out, should be series terminated if the trace is more than four inches long. (use the series termination resistor as close as possible to the qse. if the characteristic impedance of the board trace is r ohms, then use a series termination of (r-11) ohms for se_soc_out, and (r-17) ohms for se_d_out and bp_ack_out .)
pmc-sierra, inc. pm73488 qse long form data sheet pmc-980616 issue 3 5 gbit/s atm switch fabric element released datasheet 71 figure 36 shows the signal groupings for the qse. figure 36. qse pinout block diagram qse pm73488 se_soc_in(0) se_d_in(0,3:0) bp_ack_out(0) se_soc_in(31) bp_ack_out(31) se_d_out(31,3:0) se_soc_out(0) (shared between ports 0-3) se_d_out(0,3:0) bp_ack_in(0) se_soc_out(7) (shared between ports 28-31) cell_start cell_24_start stat_out se_clk se_clk_bypass /pll_bypass reset /oe add(7:0) data(7:0) /cs /rd /wr /ack /intr ram_data(15:0) ram_clk /ram_oe /ram_wr scan_tms /scan_trst scan_tck scan_tdi scan_tdo /scan_en /test_mode /iddtn bp_ack_in(31) se_d_in(31,3:0) processor interface sram interface boundary scan interface input ports output ports ram_addr(18:0) ram_parity ctrl_in
pmc-sierra, inc. pm73488 qse long form data sheet pmc-980616 issue 3 5 gbit/s atm switch fabric element released datasheet 72 6.4.1 processor interface signals table 16. processor interface signals (21 signal pins) signal name ball # # of pins type description add(7:0) aj7, ah9, ag10, af10, ak4, ah8, ag9, ak3 8in address bits 7to 0 are part of the 8-bit processor address bus. data(7:0) aj9, ah10, ag11, ae13, ae12, aj8, af11, ak6 8bi 3 data bits 7 to 0 are part of the 8-bit processor data bus. /cs ak7 1 in chip select is an active low signal that selects the device for processor access. /rd ak8 1 in read is an active low signal that selects a read cycle. /wr ah12 1 in write is an active low signal that selects a write cycle. /ack aj11 1 out 5 acknowledge is an active low signal that indicates the processor cycle is finished. /intr ag13 1 out 5 interrupt indicates an interrupt is present. 6.4.2 multicast ram interface signals table 17. multicast ram interface signals (39 signal pins) signal name ball # # of pins type description ram_add(18:0) af12, ah1, f18, c27, e23, e24, d24, f24, d26, d25, e25, a29, b30, f26, f27, e27, g25, g27, g26 19 out 5 ram address bits 18 to 0 are part of the 19-bit sram address bus. ram_data(15:0) c22, e20, a27, b24, d22, d21, e21, e22, c23, b27, a28, c25, b26, f21, b28, f22 16 bi 3 ram data bits 15 to 0 are part of the 16-bit sram data bus. ram_parity f19 1 bi 3 parity for the ram data bits. generated and checked by the qse. ram_clk b23 1 out 8 ram clock.
pmc-sierra, inc. pm73488 qse long form data sheet pmc-980616 issue 3 5 gbit/s atm switch fabric element released datasheet 73 /ram_oe c21 1 out 5 ram output enable enables all sram output signals. /ram_wr a25 1 out 5 ram write enable strobes data into external sram. note: the external ram /ce and /adsc signals are expected to be tied low and the external ram /adsp and /adv signals are expected to be tied high. 6.4.2 multicast ram interface signals table 17. multicast ram interface signals (39 signal pins) signal name ball # # of pins type description
pmc-sierra, inc. pm73488 qse long form data sheet pmc-980616 issue 3 5 gbit/s atm switch fabric element released datasheet 74 6.4.3 qse interface signals table 18. qse interface signals (364 signal pins) signal name ball # # of pins type description cell_start j6 1 in the rising edge of cell start indicates to the qse it should stop looking for the se_soc_in(31:0) on the input ports. the signal must have the following characteristics: the rising edge should come every 118 clocks exactly. also, it must be high for at least one clock and low for at least eight clocks during each 118-cycle period. thus, cell start must be high for x clocks and low for (118-x) clocks, where 1 x 110. cell_24_start c2 1 in cell 24 start indicates the start of the 4n th cell time. it should be driven high every 4n th cell_start assertions, and should match cell_start when driven high. here, n can be any integer 3 1, as long as it is the same for all the qse and qrt devices in the fabric. it is called cell_24_start because n used to be 6 (so 4n used to be 24) in some legacy systems, but that is no longer relevant. ctrl_in (or /no_data_out) e2 1 in control in is used to feed in an information packet to the qse. this information packet can be used to tell the qse not to accept any incoming cells (which is called a /no data in command) and/or tell it not to send any cells to the next stage (which is called a /no data out command). there is a software configurable mode which splits the /no data in and /no data out functionality and assigns them to separate pins. if this mode is turned on, then the ctrl_in pin performs the /no data out functionality. (the complementary function of /no data in is performed by the stat_out pin; see below.) that is, whenever ctrl_in is pulled low, the qse will not send any cells to the next stage. after reset, the above mode is on by default; that is, the ctrl_in pin is configured as /no data out.
pmc-sierra, inc. pm73488 qse long form data sheet pmc-980616 issue 3 5 gbit/s atm switch fabric element released datasheet 75 stat_out (or /no_data_in) k6 1 bi 3 on this pin, the qse periodically puts out an information packet which indicates if all multicast buffers are empty or not. there is a software configurable mode in which the stat_out pin ceases to be an output pin, and instead turns into an input pin that performs /no data in functionality. (the complementary funcion of /no data out is performed by the ctrl_in pin; see above). that is, whenever stat_out is pulled low, the qse will not accept any incoming cell. after reset, the above mode is on by default; that is, the stat_out pin is configured as /no data in. se_soc_in(31:0) ab4, ab3, w6, w5, v4, u6, u3, t1, m1, r5, r6, k1, h1, f1, d1, j5, a2, c4, c6, e9, e10, e11, c10, c12, b12, d14, a12, b15, d16, a20, c18, b22 32 in receive cell start indicates the start of a cell time. this signal precedes the first nibble of a cell by one clock. table 18. qse interface signals (364 signal pins) (continued) signal name ball # # of pins type description
pmc-sierra, inc. pm73488 qse long form data sheet pmc-980616 issue 3 5 gbit/s atm switch fabric element released datasheet 76 se_d_in(31:0, 3:0) (as follows) 128 in se_d_in ports 31-0, bits 3 to 0 are the nibble-wide data path. se_d_in31(3:0) ac3, ag1, aa5, aa4 4 in se_d_in30(3:0) ad2, ae1, y5, ac2 4 in se_d_in29(3:0) v6, y4, aa3, ab2 4 in se_d_in28(3:0) ad1, ac1, w3, y2 4 in se_d_in27(3:0) v5, aa1, w2, v3 4 in se_d_in26(3:0) u5, t6, u4, y1 4 in se_d_in25(3:0) v2, t5, w1, t4 4 in se_d_in24(3:0) u1, r1, t2, r2 4 in se_d_in23(3:0) p1, p3, r4, p4 4 in se_d_in22(3:0) n2, p5, l1, m2 4 in se_d_in21(3:0) n5, p6, n3, l2 4 in se_d_in20(3:0) g1, n4, j2, m3 4 in se_d_in19(3:0) l4, m5, h2, k3 4 in se_d_in18(3:0) n6, m6, j3, l5 4 in se_d_in17(3:0) g2, j4, k4, k5 4 in se_d_in16(3:0) h3, d2, c1, f3 4 in se_d_in15(3:0) d5, e6, e7, d6 4 in se_d_in14(3:0) f7, d7, b3, e8 4 in se_d_in13(3:0) f9, b4, f10, b5 4 in se_d_in12(3:0) a3, d9, c8, a4 4 in se_d_in11(3:0) d10, c9, b7, a6 4 in se_d_in10(3:0) b8, f12, f13, d11 4 in se_d_in09(3:0) b9, e12, a7, a8 4 in se_d_in08(3:0) b11, d13, e13, a10 4 in se_d_in07(3:0) c13, f14, e14, f15 4 in se_d_in06(3:0) a11, c14, b13, e15 4 in se_d_in05(3:0) d15, a15, a14, a16 4 in se_d_in04(3:0) b16, a19, a17, c17 4 in se_d_in03(3:0) d17, e16, b18, e17 4 in se_d_in02(3:0) b19, f16, e18, f17 4 in se_d_in01(3:0) b20, a21, a24, d18 4 in se_d_in00(3:0) c19, a23, d20, e19 4 in table 18. qse interface signals (364 signal pins) (continued) signal name ball # # of pins type description
pmc-sierra, inc. pm73488 qse long form data sheet pmc-980616 issue 3 5 gbit/s atm switch fabric element released datasheet 77 bp_ack_out(31:0) af9, aj5, ae10, aj4, ae9, ah6, af8, aj3, ag7, ae7, ah4, ag6, af7, af6, ag5, ak2, aj1, af4, ae5, ad5, ae4, ag3, ad6, ad4, ah2, ac5, ae3, ab6, ag2, aa6, af2, ab5 32 out 5 acknowledge outputs 31 to 0 assert an acknowledge toward the previous qse or qrt for unicast cells. it also carries backpressure information for multicast cells. se_soc_out(7:0) aj15, ak24, ag21, ag25, ab27, ac30, t27, n26 8out 8 transmit cell start indicates the start of a cell time. this signal precedes the first nibble of a cell by one clock. table 18. qse interface signals (364 signal pins) (continued) signal name ball # # of pins type description
pmc-sierra, inc. pm73488 qse long form data sheet pmc-980616 issue 3 5 gbit/s atm switch fabric element released datasheet 78 se_d_out(31:0, 3:0) (as follows) 128 out 5 se_d_out ports 31-0, bits 3 to 0 are 32 nibble-wide output ports. se_d_out31(3:0) ae14, ah13, aj12, ak10 4out 5 se_d_out30(3:0) ak11, ag14, ae15, af14 4out 5 se_d_out29(3:0) ak12, af15, aj13, ah14 4out 5 se_d_out28(3:0) ak16, ak14, ak15, ag15 4out 5 se_d_out27(3:0) ag16, ah17, ak17, ak19 4out 5 se_d_out26(3:0) af17, aj18, af16, ag17 4out 5 se_d_out25(3:0) af18, ae16, aj19, ak20 4out 5 se_d_out24(3:0) ak21, aj20, ah18, ae17 4out 5 se_d_out23(3:0) ak23, ah19, aj22, ag18 4out 5 se_d_out22(3:0) ah21, aj23, af19, ag20 4out 5 se_d_out21(3:0) ah22, ae19, ae18, ak25 4out 5 se_d_out20(3:0) ag22, aj24, ak27, af20 4out 5 se_d_out19(3:0) aj27, ah23, af22, af21 4out 5 se_d_out18(3:0) ae21, aj26, ah25, ak28 4out 5 se_d_out17(3:0) af23, ah27, ae22, aj28 4out 5 se_d_out16(3:0) ag26, ae24, ag24, af24 4out 5 table 18. qse interface signals (364 signal pins) (continued) signal name ball # # of pins type description
pmc-sierra, inc. pm73488 qse long form data sheet pmc-980616 issue 3 5 gbit/s atm switch fabric element released datasheet 79 6.4.4 boundary scan signals se_d_out15(3:0) ae27, ad26, ae26, ak29 4out 5 se_d_out14(3:0) ah29, ad27, ad25, ag28 4out 5 se_d_out13(3:0) ag29, ab25, ae28, ac26 4out 5 se_d_out12(3:0) ah30, ab26, af29, aa25 4out 5 se_d_out11(3:0) aa27, aa26, ag30, ac28 4out 5 se_d_out10(3:0) y26, ae30, ad29, ab28 4out 5 se_d_out09(3:0) y27, v25, w25, ac29 4 out 5 se_d_out08(3:0) ad30, w26, ab29, aa28 4out 5 se_d_out07(3:0) v26, v27, y29, w28 4 out 5 se_d_out06(3:0) u25, v28, w29, aa30 4 out 5 se_d_out05(3:0) y30, u27, t25, u26 4 out 5 se_d_out04(3:0) w30, t26, v29, u28 4 out 5 se_d_out03(3:0) t29, r30, u30, t30 4 out 5 se_d_out02(3:0) p28, p30, m30, r29 4 out 5 se_d_out01(3:0) n29, r26, p27, r27 4 out 5 se_d_out00(3:0) r25, m29, l30, p26 4 out 5 bp_ack_in(31:0) h26, d28, j25, c29, k25, e29, f28, c30, d29, h28, j26, k26, k27, j27, g29, d30, l26, j28, m25, n25, f30, k28, h29, m26, l27, h30, m28, j29, n27, g30, k30, l29 32 in acknowledge inputs 31 to 0 receive an acknowledge from the previous qse or qrt for unicast cells. it also carries backpressure information for multicast cells. table 19. boundary scan signals (8 signal pins) signal name ball # pin # type description scan_tck g4 1 in scan test clock is an independent clock used to drive the internal boundary scan test logic. (normal operation = v dd through a pull-up resistor.) table 18. qse interface signals (364 signal pins) (continued) signal name ball # # of pins type description
pmc-sierra, inc. pm73488 qse long form data sheet pmc-980616 issue 3 5 gbit/s atm switch fabric element released datasheet 80 scan_tdi b1 1 in scan test data input is the serial input for boundary scan test data and instruction bits. (normal operation = v dd through a pull-up resistor.) scan_tdo f5 1 out 6 scan test data output is the serial output for boundary scan test data. scan_tms f4 1 in scan test mode select controls the operation of the internal boundary scan test logic. (normal operation = v dd through a pull-up resistor.) /scan_trst e4 1 in scan test reset is used to reset the internal boundary scan test logic. (normal operation = v dd through a pull-up resistor.) /scan_en g6 1 in scan test enable is used to enable the internal scan test logic. (normal operation = v dd through a pull-up resistor.) /test_mode n28 1 in test mode. (normal operation = v dd through a pull-up resistor.) table 19. boundary scan signals (8 signal pins) (continued) signal name ball # pin # type description
pmc-sierra, inc. pm73488 qse long form data sheet pmc-980616 issue 3 5 gbit/s atm switch fabric element released datasheet 81 6.4.5 miscellaneous signals table 20. miscellaneous signals (8 signal pins) signal name ball # pin # type description se_clk aj16 1 in qse clock is the main qse clock. se_clk_bypass af25 1 in qse bypass clock is the clock used when the phase locked loop (pll) is bypassed. /oe d3 1 in output enable is an active low signal that enables the drivers on device outputs. reset af13 1 in reset is an active high signal used to initialize or re- initialize the device. se_clk must be present for the reset to take effect. /pll_bypass p25 1 in bypass pll, and use clock from se_clk_bypass for the qse instead of se_clk. (normal operation = v dd through a pull-up resistor.) pll_vdd aj30 1 in pll power. connect to v dd . pll_vss af27 1 in pll ground. connect to gnd. /iddtn g5 1 in global output disable. (normal operation = gnd.) vdd d8, b6, c11, a9, b14, b17, c20, a22, d23, b25, e26, c28, a30, h27, f29, l28, j30, p29, u29, y28, ab30, ac27, ae29, af26, ah28, ak30, ag23, aj25, ah20, ak22, aj17, aj14, ah11, ak9, ag8, aj6, af5, ah3, ak1, ac4, ae2, y3, ab1, u2, p2, l3, j1, h4, f2, e5, c3, a1, 52 in supply voltage 3.3 v 10%.
pmc-sierra, inc. pm73488 qse long form data sheet pmc-980616 issue 3 5 gbit/s atm switch fabric element released datasheet 82 vss n1, m4, k2, g3, e1, e3, f6, d4, b2, u21, p21, m21, aa19, aa17, k17, aa14, k14, k12, w10, u10, p10, k19, m10, aa12, w21, l11, m12, p12, u12, w12, y11, m14, p14, u14, w14, m17, p17, u17, w17, l20, m19, p19, u19, w19, y20, c5, c7, a5, d12, b10, a13, c15, c16, a18, d19, b21, c24, a26, c26, f25, d27, b29, e28, g28, e30, m27, k29, n30, r28, t28, v30, w27, aa29, ad28, af30, af28, ae25, ag27, aj29, ah26, ah24, ak26, ag19, aj21, ak18, ah16, ah15, ak13, ag12, aj10, ah7, ak5, ah5, af3, ae6, ag4, aj2, ad3, af1, w4, aa2, v1, t3, r3 104 in ground. table 20. miscellaneous signals (8 signal pins) signal name ball # pin # type description
pmc-sierra, inc. pm73488 qse long form data sheet pmc-980616 issue 3 5 gbit/s atm switch fabric element released datasheet 83 6.4.6 total pin count table 21. pin allocations signal name pin # type description total processor interface signals 21 total multicast ram signals 39 total qse interface signals 364 total boundary scan signals 8 total miscellaneous signals 8 total signal pins 440 v dd 52 in supply voltage 3.3 v 10%. gnd 104 in ground. total pins 596
pmc-sierra, inc. pm73488 qse long form data sheet pmc-980616 issue 3 5 gbit/s atm switch fabric element released datasheet 84 7 physical characteristics . table 22. absolute maximum ratings symbol parameter conditions min max unit v dd supply voltage with respect to gnd -0.3 3.9 v i out dc output current, per pin all outputs -12 12 ma t stg storage temperature -65 125 c t j junction operating temperature -40 125 c t r input rise time 10 ns t f input fall time 10 ns esd tolerance 1kv latch-up current 80 ma table 23. recommended operating conditions symbol parameter conditions min typ max unit v dd supply voltage 3.0 3.3 3.6 v v i input voltage v ss - 0.5 v dd v dd + 0.3 v t a ambient operating temperature see note about junction operating temperature after table 26 on page 85 . -40 25 85 c t r input rise time 1.5 2 ns t f input fall time 1.5 2 ns table 24. dc operating conditions symbol parameter conditions min typ max unit v ih high-level ttl input voltage 5 v tolerant inputs 2.2 v dd 5.5 v v il low-level ttl input voltage gnd-0.3 0.0 0.8 v v oh high-level ttl output voltage |i oh | specified dc drive current (in signal descriptions section) 2.4 v v ol low-level ttl output voltage |i ol | specified dc drive current (in signal descriptions section) 0.4 v i typ typical operating current 66 mhz clock rate 900 ma
pmc-sierra, inc. pm73488 qse long form data sheet pmc-980616 issue 3 5 gbit/s atm switch fabric element released datasheet 85 note: the junction temperature must be kept below 125c while the device is operating. table 25. capacitance symbol parameter conditions min max unit c in input capacitance 1.5 6 pf c out output capacitance 1.5 6 pf c load load capacitance to meet timing on any output signal 30 pf notes: capacitance measured at 25 o c. sample tested only. table 26. estimated package thermal characteristics symbol parameter condition typ unit q jc junction-to-case thermal resistance 2.5 c/watt q ja junction-to-ambient thermal resistance still air 12.0 c/watt q ja junction-to-ambient thermal resistance 200 lfpm 10.2 c/watt q ja junction-to-ambient thermal resistance 400 lfpm 9.4 c/watt q ja junction-to-ambient thermal resistance 600 lfpm 8.9 c/watt
pmc-sierra, inc. pm73488 qse long form data sheet pmc-980616 issue 3 5 gbit/s atm switch fabric element released datasheet 86 8 timing diagrams all signal names are described in section 6.4 pin descriptions starting on page 70 . unless otherwise indicated, all output timing delays assume a capacitive loading of 30 pf and that the internal pll is enabled. the use of the internal pll is controlled through the /pll_bypass signal. it is recommended that the internal pll remains enabled 8.1 microprocessor timing a microprocessor cycle starts when the chip select (/cs) and either read (/rd) or write (/wr) are asserted. during read cycles, the qse asserts /ack to indicate data on the data bus is valid, and during write cycles the qse asserts / ack to indicate the write has finished and data can be removed from the bus. the microprocessor can terminate the current cycle at anytime. as shown in figure 37, the qse stops driving the data bus and deasserts the /ack control line when the cycle terminates. the current cycle terminates when the chip select is deasserted, or when both read and write are deasserted. a new cycle can start once the /ack has been deasserted. if the cycle was terminated prema- turely before the /ack was asserted, then a new microprocessor cycle can start after one clock cycle. note: asserting both read and write lines together while the chip select is asserted (/rd = 0, /wr = 0, and / cs = 0) will cause the device to operate in an undefined manner. figure 37. microprocessor timing table 27. microprocessor timing symbol parameter conditions min max unit tvk /ack valid after /cs, /rd, or / wr, whichever is low last /ack 2 118 se_clk cycles tqk se_clk-to-output delay /ack 1 10 ns twcy tvdk tqk tvk tvk thc thc tqk thc thc tqd thc thc tvd thd tva tva tha tva tha se_clk /cs /rd /wr /ack data(7:0) add(7:0)
pmc-sierra, inc. pm73488 qse long form data sheet pmc-980616 issue 3 5 gbit/s atm switch fabric element released datasheet 87 8.2 ram timing the ram interface is a synchronous interface, with respect to the ram_clk. each read or write operation lasts for at least two clock cycles because of the internal 32-bit data bus. recall that the ram_data bus is covered by one bit of parity, named ram_parity; this parity bit signal follows the same timing constraints and timing guarantees as the rest of the data bus. tqd se_clk-to-output delay data(7:0) 1 13.5 ns tvdk data valid prior to /ack assertion data(7:0) se_clk cycle - 10.3 ns tvd data valid after /cs or /wr, whichever is low last data(7:0) 1 se_clk cycle tva address valid after /cs, /rd, or /wr, whichever is low last add(7:0) 1 se_clk cycles tha address hold after /ack assertion add(7:0) 0 ns thd data hold after /ack assertion for write cycle data(7:0) 0 ns thc hold time after /cs, /rd, or / wr, whichever is high first /ack, data(7:0) 1.2 ns twcy wait time between two consecutive cycles /cs, /rd, /wr 1 se_clk cycles figure 38. ram interface table 28. ram interface timing symbol parameter conditions min max unit tck se_clk to ram_clk ram_clk 0.5 2.5 ns table 27. microprocessor timing (continued) symbol parameter conditions min max unit tck tsd thd tq tq tqa tqa tq se_clk ram_clk /ram_wr /ram_oe ram_add ram_data
pmc-sierra, inc. pm73488 qse long form data sheet pmc-980616 issue 3 5 gbit/s atm switch fabric element released datasheet 88 8.3 qse interface timing figure 39 shows the bit-level timing for the qse. tq ram_clk-to-output delay /ram_wr, /ram_oe, ram_data 1.5 9 ns tsd ram_clk setup time ram_data 5.2 ns thd ram_clk hold time ram_data 0 ns tqa ram_clk-to-output delay ram_add 1.5 10 ns figure 39. qse bit-level timing symbol parameter signals min max unit fseclk frequency of se_clk se_clk 35 a 66 mhz tctsu control signal setup cell_start, cell_24_start 8.0 ns tctho control signal hold cell_start, cell_24_start 0 ns tseq output delay from se_clk se_d_out (15 pf), bp_ack_out(31:0), se_soc_out(7:0) b 16ns output delay skew * se_d_out(0,3:0) and se_soc_out se_d_out(1,3:0) and se_soc_out se_d_out(2,3:0) and se_soc_out se_d_out(3,3:0) and se_soc_out 1.9 ns input delay skew * se_d_in(0,3:0) and se_soc_in(0) se_d_in(1,3:0) and se_soc_in(1) se_d_in(2,3:0) and se_soc_in(2) se_d_in(3,3:0) and se_soc_in(3) 3.5 ns * when the phase aligners are turned on, tsesu and tseho are no longer defined. however, the maximum input and output skew and jitter on these signals with respect to the se_soc_in is constrained to specification listed in this table. table 28. ram interface timing (continued) symbol parameter conditions min max unit tctsu tsesu fseclk fseclk tseho tseq tctho tseq se_clk se_d_in(31:0, 3:0), bp_ack_in(31:0) se_d_out(31:0,3:0), bp_ack_out(31:0) cell_start, cell_24_start se_soc_out(7:0)
pmc-sierra, inc. pm73488 qse long form data sheet pmc-980616 issue 3 5 gbit/s atm switch fabric element released datasheet 89 8.4 miscellaneous timing timing for the ctrl_in, stat_out, test_mode, iddtn and debug(1:0) signals is shown in table 29. figure 40 shows the reset pin (reset) timing. the reset signal must be asserted for a minimum time ( tres ) to be properly processed internal to the qse. the qse remains in reset while reset is asserted, and starts performing normally after trstproc . a. for the phase aligners to lock. b. in real applications the output skew will be lower than 1.9ns. the reason for this is as follows. when all pins are equally loaded, se_soc_out is faster than all the se_d_outs by (upto) 1.9ns. however, in real applications se_soc_out will have fan-out of four, and hence will be loaded four times as much as the other pins. this will slow down se_soc_out and hence lower the output skew. table 29. ctrl_in, stat_out, test_mode and debug timing symbol parameter signals min max unit tdasu control signal setup stat_out (when it behaves as i/p) 4 ns tdasu control signal setup ctrl_in 4 ns tdaho control signal setup test_mode 10 ns tdaho control signal setup iddtn 10 ns tdaho control signal hold stat_out (when it behaves as i/p) 0 ns tdaho control signal hold ctrl_in 0 ns tdaho control signal hold test_mode 10 ns tdaho control signal hold iddtn 10 ns tdaq output delay from se_clk stat_out (when it behaves as o/p) 1 10 ns tdeq output delay from se_clk debug(1,0), 1.5 14 ns figure 40. reset timing symbol parameter signals min max unit tres reset assertion time reset 10 se_clk periods trstproc reset processing time reset 2 3 se_clk periods trstproc trstproc tres tres se_clk reset cell_start(i)
pmc-sierra, inc. pm73488 qse long form data sheet pmc-980616 issue 3 5 gbit/s atm switch fabric element released datasheet 90 note: reset assertion and deassertion is asynchronous to the clock. timing information for the soc, bp, and ack is given in table 30. figure 41 shows the timing for the jtag port. the /scan_trst signal is asynchronous to scan_tck. table 30. valid window timing symbol parameter min max unit vsoc soc valid window local_cell_start - 8 local_cell_start se_clk periods vbprec valid window when bp is accepted by qse se_soc_out + 0 local_cell_start + 60 se_clk periods vbpgen valid window when bp is generated by qse local_cell_start + 15 (but in early bp mode: local cell_start + 0 see bp_control_register on page 109) local_cell_start + 35 (but in early bp mode: local_cell_start + 15 seebp_control_register on page 109) se_clk periods vack valid window when ack is accepted by qse se_soc_out + 0 (next cell times) local_cell_start - 8 se_clk periods figure 41. jtag timing symbol parameter signals min max unit scan_tck frequency 10 mhz tch scan_tck high 40 ns tjres tjres tch tch tjsu tjsu tjh tjh tcl tcl tqj tqj scan_trst(i) scan_tck(i) scan_tms(i) scan_tdi(i) scan_tdo(o)
pmc-sierra, inc. pm73488 qse long form data sheet pmc-980616 issue 3 5 gbit/s atm switch fabric element released datasheet 91 tcl scan_tck low 40 ns tjh scan_tck hold time scan_tms, scan_tdi 20 ns tjsu scan_tck setup time scan_tms, scan_tdi 20 ns tjres /scan_trst low 40 ns tqj scan_tck-to-output delay /scan_trst-to-output delay scan_tdo 20 ns symbol parameter signals min max unit
pmc-sierra, inc. pm73488 qse long form data sheet pmc-980616 issue 3 5 gbit/s atm switch fabric element released datasheet 92 9 microprocessor ports 9.1 microprocessor ports summary notes: ? all read/write port bits marked not used must be written with the value 0 to maintain software com- patibility with future versions. ? all port bits marked reserved should not be written. software modifications to these locations after setup may cause incorrect operation. ? for 16-bit registers at addresses x and ( x +1), bit 15 is address x bit 7 and bit 0 is address ( x +1) bit 0. ? for 32-bit registers at addresses x to ( x +3), bit 31 is address x bit 7 and bit 0 is address ( x +3) bit 0. for example, the input_port_enable register. ? for 128-bit registers at addresses x to ( x +f h ), nibble 31 is address x bits 7 to 4 and nibble 0 is address ( x +f h ) bits 3 to 0. for example, the input_marked_cells_count register. ? registers marked with a t should only be modified while the chip is in software reset. table 31. microprocessor ports summary address (in hex) name read or write description chip control/status registers 0 revision r contains the device revision number (namely, 01 h ). 1 chip_mode r/wt assorted chip-configuration bits. 2-3 multicast_group_index r/w multicast group to be modified or read. 4-7 multicast_group_vector r/w set of destinations comprising the multicast group. 8 multicast_group_op r/w operation to be performed. 9-a uc/mc_fairness_register r/w unicast/multicast behavior for cells of the same priority. b extended_chip_mode r/wt extended chip mode c multicast_group_index_msb r/w highest byte of multicast group to be modified or read. d-f reserved port control/status registers 10-13 input_port_enable r/w enable input ports and associated interrupts. 14-17 output_port_enable r/w enable output ports and associated interrupts. 18-27 input_marked_cells_count r count of marked cells arriving at inputs. 28-37 output_marked_cells_count r count of marked cells leaving at outputs. 38-3b parity_error_present r parity error status on inputs during the last cell time. 3c-3f parity_error_latch r indicates if any parity errors have occurred since the last read. 40-43 parity_error_int_mask r/w enables/disables interrupt due to parity error.
pmc-sierra, inc. pm73488 qse long form data sheet pmc-980616 issue 3 5 gbit/s atm switch fabric element released datasheet 93 44-47 se_input_port_fail_present r indicates absence of special pattern on soc or invalid cell present code on data lines or invalid idle cell code on data lines during the last cell time. 48-4b se_input_port_fail_latch r indicates if an se_input_port_fail has occurred since the last read. 4c-4f bp_ack_fail_present r indicates absence of special coding on bp_ack_in line on output ports during the last cell time. 50-53 bp_ack_fail_latch r indicates if a bp_ack_fail has occurred since the last read. 54-57 bp_remote_fail_present r indicates absence of back pressure on bp_ack_in line on output ports during the last cell time. 58-5b bp_remote_fail_latch r indicates if a bp_remote_fail condition has occurred since the last read. 5c-7f reserved switch control/status registers 80 control_register r/wt various switch parameters. 81 interrupt_status_register r identifies if an interrupt condition is present. 82 multicast_aggregate_outpu t_mode r/wt aggregate mode for multicast cells. 83 unicast_aggregate_output_ mode r/wt aggregate mode for unicast cells. 84 switch_fabric_row r/wt row number in switch fabric. 85 switch_fabric_column r/wt column number in switch fabric. 86 cell_start_offset r/wt offset between internal and external cell_start signals. 87 bp_control_register r/wt control backpressure functionality. 88 ack_payload r/w payload for ack packet when ack needs to be generated by the qse for parity fail and regular congestion. 89 gang_dead_ack r/w payload for ack packet when ack needs to be generated by the qse because the entire gang is dead. 8a extended_switch_mode rt extended switch control register. 8b-ef reserved table 31. microprocessor ports summary (continued) address (in hex) name read or write description
pmc-sierra, inc. pm73488 qse long form data sheet pmc-980616 issue 3 5 gbit/s atm switch fabric element released datasheet 94 9.2 note on error detection and reporting the qse detects six classes of errors and each error in every class is reported using two bits: ? error_present: there is an error at the present moment ? error_latched: there was an error sometime in the past, between now and the last time this register was read. of these two bits, errors latched in the error_latched registers can be further used to generate interrupts to the micro- processor. the six detected classes of errors fall into two categories: category 1: errors that can be associated with an input or output port. errors in this category are only detected if the corresponding port is enabled. ? input port failed: this means that one of the soc_in or data_in wires is stuck or glitchy. the error_present register is at address 44-47, and the error_latched register is at address 48-4b. you can stop checking for this error by turning off the appropriate input ports using the register at address 10-13. ? bpack failed: this means that one of the bpack_in wires is stuck or glitchy. the error_present register is at address 4c-4f, and the error_latched register is at address 50-53. so you can stop checking for this error by turning off the appropriate output port using the register at address 14-17. ? remote failure: this means that the downstream qse did not sent a bp packet on some bpack_in wire during some cell-time. by implication, it means that one of the soc_out or data_out wires is stuck or glitchy (to which the downstream qse responds by withholding the bp packet). the error_present register is at address 54-57, and the error_latched register is at address 58-5b. you can stop checking for this error by turning off the appropriate output port using the register at address 14-17. ? parity error in a cell. the error_present register is at address 38-3b, and the error_latched register is at address 3c-3f. you can stop checking for this error by turning off the appropriate input ports using the register at address 10-13. a separate set of registers at address 40-43 allow you to disable interrupts due to this error. you can also globally disable all parity checks on input ports using the chip_mode register (bit 6). each of the above four classes of errors has a "summary" bit in the interrupt status register (isr) at address 81. the summary bit for a class is set if any enabled error is latched in that class. an actual interrupt to the microprocessor (due to these classes of errors) will be generated if any of the four summary bits in the isr are set and if the global interrupt mask is enabled. category 2: errors in this category are global to the entire chip. ? cstart is out of lock. the error_present register is at address 80 (bit 7), and the error_latched register is at address 8a (bit 0). you can turn off the interrupt from this error using the register at address 80 (bit 6). if this error is causing an interrupt, this is indicated by bit 4 of the isr (address 81). ? parity error in external mc connection ram. there is no error_present register. the error_latched register is at address b(bit 6). you can turn off the parity check using the register at address b(bit 4) and you can disable interrupts due to this error using address b(bit 5). this error will cause an interrupt if it has been latched and if interrupts from this error have not been disabled using the register at address b (bit 5). 9.3 microprocessor ports bit definitions note: the bits reset to 0 b unless otherwise indicated.
pmc-sierra, inc. pm73488 qse long form data sheet pmc-980616 issue 3 5 gbit/s atm switch fabric element released datasheet 95 9.3.1 revision this register contains the device revision number. address: 0 h type: read only format: refer to the following table. 9.3.2 chip_mode address: 1 h type: read/write format: refer to the following table. field (bits) description revision (7:0) revision number of the qse device. revision numbers start at 0. field (bits) description enable_stat_pins (7) 1 enable statout and ctrlin pin functionality 0 statout behaves like no data in, and ctrl in behaves like no data out. parity_check (6) 1 parity checks on cell header disabled. 0 normal operation. /no_data_out (5) current value at the /no_data_out pin. /no_data_in (4) current value at the /no_data_in pin. multicast_mode (3) 1 external ram present. 0 no external ram. chip_hardware_reset (2) 1 writing a one to this bit will put the chip is in hardware reset (except the processor interface, which remains untouched). 0 writing a zero to this bit will take the chip out of hardware reset. upon pin-reset, this bit comes up as a one. a zero must be explicitly written to this bit before the chip can function normally. switch_mode (1) 1 double switch mode. 0 single switch mode. reserved (1:0) write with a 0 to maintain future software compatibility.
pmc-sierra, inc. pm73488 qse long form data sheet pmc-980616 issue 3 5 gbit/s atm switch fabric element released datasheet 96 9.3.3 multicast_group_index_register address: 2-3 h type: read/write format: refer to the following table. 9.3.4 multicast_group_vector_register address: 4-7 h type: read/write format: refer to the following table. field (bits) description mc_add (15:0) multicast group index to be used by multicast_group_op (refer to section 9.3.5 multicast_group_op on page 97 ). this register has bits 15 to 0 of the index. the multicast_group_index_msb register has the remaining. field (bits) description mc_group (31:0) multicast group vector (mgv) data to be used by multicast_group_op (refer to section 9.3.5 multicast_group_op on page 97 ). address 45 h bit 7 corresponds to the highest register bit, and 42 h bit 0 corresponds to the lowest register bit. depending on the multicast gang mode, only certain bits are active, and the active bits are as follows: gang 1 mask ffffffff h gang 2 mask 0f0f0f0f h gang 4 mask 03030303 h 1 enables the transmission of a cell on the multicast group corresponding to the active bit number. 0 disables the transmission of a cell on the multicast group corresponding to the active bit number.
pmc-sierra, inc. pm73488 qse long form data sheet pmc-980616 issue 3 5 gbit/s atm switch fabric element released datasheet 97 9.3.5 multicast_group_op address: 8 h type: read/write format: refer to the following table. 9.3.6 uc/mc_fairness_register address: 9-a h type: read/write format: refer to the following table. 9.3.7 extended_chip_mode address: b h type: read/write field (bits) description not used (7:2) write with a 0 to maintain future software compatibility. inc_bit (1) increment bit. 1 autoincrement multicast_group_index_register (refer to section 9.3.3 multicast_group_index_register on page 96 ) after each operation. 0 leave multicast_group_index_register unchanged. operation_bit (0) operation bit. 1 enables the write of multicast_group_vector_register to the multicast group vector equal to the address referenced by multicast_group_index_register. 0 enables the read of multicast_group_vector_register from the multicast group vector equal to the address referenced by multicast_group_index_register. field (bits) description upper ports (15:8) suppose a uc cell and an mc cell of the same priority are contending for the same output port, where the output port number is between 31 and 16. if x bits are set, then the uc cell has an x/8 probability of winning over the mc cell. for example, if (any) 4 of the 8 bits are set, then a tie is broken randomly with a 50-50 chance of either one winning. if none of the bits are set, then mc always wins, and if all the bits are set then uc always wins. this register resets to 3a h . lower ports (7:0) same as above, except this register controls output ports between 15 and 0. another difference is that this register resets to a3 h .
pmc-sierra, inc. pm73488 qse long form data sheet pmc-980616 issue 3 5 gbit/s atm switch fabric element released datasheet 98 format: refer to the following table. 9.3.8 multicast_group_index_msb address: c h type: read/write format: refer to the following table. 9.3.9 input_port_enable address: 10-13 h field (bits) description not used (7) write with a 0 to maintain future software compatibility. ram_parity_err_sensed (6) 1: a parity error was sensed in the external multicast ram 0: no parity error was sensed or parity is not enabled ram_parity_int_enable (5) 1: enable interrupt on external multicast vector ram parity error 0: no interrupt on ram parity error ram_parity_enable (4) 1: enable parity checking for the external multicast vector ram 0: disable parity checking for the external multicast vector ram not used (3:1) write with a 0 to maintain future software compatibility. short_tag_enable 1: rotate only 5 nibbles of the routing tag. 0: rotate all 8 nibbles of the routing tag. when the qse receives a unicast cell, it looks at the initial portion of the cells routing tag, and interprets it to be the destination gang of the cell. before sending the cell out on that destination, the qse cyclically shifts the routing tag leftwards. the purpose of this shift is to move new bits into the initial portion of the routing tag, thus making the routing tag suitable for use by the next-stage qse. the amount of the rotation is equal to (5 - uc output gang mode) bits. (for a discussion on uc output gang mode, see section 9.3.25 unicast_aggregate_output_mode on page 106.) if short_tag_enable is set to 1, then only 5 nibbles are rotated. hence, the last 3 nibbles are left untouched, and they could potentially be used by the traffic manager to send diagnostic information. the qrt currently does not *not* use these 3 nibbles for anything. therefore, when the qse is used in conjunction with the qrt, there is no advantage to short tags, and the short_tag_enable bit may remain at the reset-default value of 0. field (bits) description mgi_msb (1:0) bits 17 and 16 of the multicast group index. use along with the multicast_group_index_register
pmc-sierra, inc. pm73488 qse long form data sheet pmc-980616 issue 3 5 gbit/s atm switch fabric element released datasheet 99 type: read/write format: refer to the following table. 9.3.10 output_port_enable address: 14-17 h type: read/write format: refer to the following table. 9.3.11 input_marked_cells_count address: 18-27 h type: read only format: refer to the following table. 9.3.12 output_marked_cells_count address: 28-37 h type: read only field (bits) description (31:0) bit x : 1 enable input port x . 0 disable input port x and interrupts due to se_input_port_fail_present (refer to section 9.3.16 se_input_port_fail_present on page 101 ). field (bits) description (31:0) bit x : 1 enable output port x . 0 disable output port x and interrupts due to bp_ack_fail_present (refer to section 9.3.18 bp_ack_fail_present on page 102 ) and bp_remote_fail_present (refer to section 9.3.20 bp_remote_fail_present on page 103 ). field (bits) description nibble 31 - nibble 0 nibble x : number of cells mod 16 on input port x that had tag(9,1) set to 1. all marked cells that enter on that port will be counted, even if they are discarded later on due to other reasons (e.g. multicast cell with parity errored header, or a multicast cell sent in violation of back-pressure.)
pmc-sierra, inc. pm73488 qse long form data sheet pmc-980616 issue 3 5 gbit/s atm switch fabric element released datasheet 100 format: refer to the following table. 9.3.13 parity_error_present address: 38-3b h type: read only format: refer to the following table. 9.3.14 parity_error_latch address: 3c-3f h type: read only format: refer to the following table. 9.3.15 parity_error_int_mask address: 40-43 h type: read/write format: refer to the following table. field (bits) description nibble 31 - nibble 0 nibble x : number of cells mod 16 on output port x that had tag(9,1) set to 1. field (bits) description (31:0) indicates if a parity error was present on the input port data lines during the last cell time. bit x : 1 error detected on input port x . 0 no error on input port x . field (bits) description (31:0) indicates if a parity error occurred on an input port since the last time this register was read. bit x : 1 error detected on input port x . 0 no error on input port x . reset to 0 on read. field (bits) description (31:0) bit x : 1 enable interrupt due to parity condition latched for input port x . 0 disable interrupt due to parity condition latched for input port x .
pmc-sierra, inc. pm73488 qse long form data sheet pmc-980616 issue 3 5 gbit/s atm switch fabric element released datasheet 101 9.3.16 se_input_port_fail_present address: 44-47 h type: read only format: refer to the following table. field (bits) description (31:0) bit x: 1 indicates that one or more of the following conditions were true for input port x during the last cell time: - special pattern on se_soc_in is absent. - presence of an invalid cell present code. - presence of an invalid idle cell code. 0 normal.
pmc-sierra, inc. pm73488 qse long form data sheet pmc-980616 issue 3 5 gbit/s atm switch fabric element released datasheet 102 9.3.17 se_input_port_fail_latch address: 48-4b h type: read only format: refer to the following table. 9.3.18 bp_ack_fail_present address: 4c-4f h type: read only format: refer to the following table. 9.3.19 bp_ack_fail_latch address: 50-53 h type: read only format: refer to the following table. field (bits) description (31:0) bit x : 1 an se_input_port_fail_present (refer to section 9.3.16 se_input_port_fail_present on page 101 ) has occurred on input port x since the last time this register was read. 0normal. reset to 0 on read. field (bits) description (31:0) bit x : 1 indicates absence of special pattern on the bp_ack line for output x . 0normal field (bits) description (31:0) bit x : 1 a bp_ack_fail_present has occurred on output x since the last time this register was read. 0normal. reset to 0 on read.
pmc-sierra, inc. pm73488 qse long form data sheet pmc-980616 issue 3 5 gbit/s atm switch fabric element released datasheet 103 9.3.20 bp_remote_fail_present address: 54-57 h type: read only format: refer to the following table. 9.3.21 bp_remote_fail_latch address: 58-5b h type: read only format: refer to the following table. 9.3.22 control_register address: 80 h type: read/write format: refer to the following table. field (bits) description (31:0) bit x : 1 indicates absence of back pressure on bp_ack line for output x during last cell time. 0normal. field (bits) description (31:0) bit x : 1 indicates a bp_remote_fail_present (refer to section 9.3.18 bp_ack_fail_present on page 102 ) has occurred on output x since the last time this register was read. 0normal. reset to 0 on read. field (bits) description cell_start_in_lock (7) 1 cell_start is in lock. 0 cell_start is not in lock. this bit may be viewed as the complemented form of the error_present indicator cell_start_out_of_lock_present. the corresponding error_latched indicator may be found in section 9.3.32 extended_switch_mode on page 110. for a general discussion on error_present and error_latched indicators, see section 9.2 note on error detection and reporting on page 94. cell_start_out_of_lock_ int_mask (6) 1 interrupt when cell_start out of lock. 0 no interrupt when cell_start is out of lock.
pmc-sierra, inc. pm73488 qse long form data sheet pmc-980616 issue 3 5 gbit/s atm switch fabric element released datasheet 104 reserved (5) write with a 0 to maintain future software compatibility. phase_aligner_mode (4) 1 phase aligner off. 0 phase aligner on. this bit should remain cleared (i.e. 0) for normal operation. reserved (3) write with a 0 to maintain future software compatibility. reserved (2) write with a 0 to maintain future software compatibility. int_enable (1) 1 global interrupt enabled. 0 global interrupt disabled. the interrupt will remain asserted as long as this bit is set and at least one of the bits in the interrupt status register is set. unfortunately, setting this bit to 0 does not disable interrupts due to ram parity-error and cstart out-of-lock. they need to be disabled separately. ram parity-error interrupt may be disabled using bit 5 of extended_chip_mode on page 97. cstart out-of-lock interrupt may be disabled using bit 6 of control_register on page 103. sw_reset (0) 1 writing a one to this bit will put the chip in software reset. this means that the processor interface will remain untouched, and the remaining blocks in the chip will be reset only some portion of their state (depending on the discretion of the designer). 0 writing a zero to this bit will take the chip out of software reset. upon pin-reset, this bit comes up as a one. a zero must be explicitly written to this bit before the chip can function normally. field (bits) description
pmc-sierra, inc. pm73488 qse long form data sheet pmc-980616 issue 3 5 gbit/s atm switch fabric element released datasheet 105 9.3.23 interrupt_status_register address: 81 h type: read only format: refer to the following table. this register can be used to check status in polled mode even if interrupts are disabled in the control_register (refer to section 9.3.22 control_register on page 103 ). 9.3.24 multicast_aggregate_output_and_input_modes address: 82 h type: read/write note: also called multicast gang mode register format: refer to the following table. field (bits) description not used (7:4) driven with a 0. mask on reads to maintain compatibility with future versions. cstart_out_of_lock (4) cell_start out-of-lock interrupt is enabled and cell_start out-of- lock latch is on. parity_error (3) an input in which parity_error_int_mask (refer to section 9.3.15 parity_error_int_mask on page 100 ) is enabled has a latched parity error. input_port_fail (2) an enabled input has a latched se_input_port_fail_latch (refer to section 9.3.17 se_input_port_fail_latch on page 102 ). bp_ack_fail (1) an enabled output has a latched bp_ack_fail_latch (refer to section 9.3.21 bp_remote_fail_latch on page 103). bp_remote_fail (0) an enabled output has a latched bp_remote_fail_latch (refer to section 9.3.21 bp_remote_fail_latch on page 103 ). field (bits) description not used (7) write with a 0 to maintain future software compatibility.
pmc-sierra, inc. pm73488 qse long form data sheet pmc-980616 issue 3 5 gbit/s atm switch fabric element released datasheet 106 9.3.25 unicast_aggregate_output_mode address: 83 h type: read/write note: also called unicast gang mode register multicast_agg_out (6:4) selects aggregate of n. that is, n consecutive outputs are treated as a single output by the switch for multicast traffic. (2:0) = 3 - 7 are invalid. (2:0) = 2, n = 4. (2:0) = 1, n = 2. (2:0) = 0, n = 1. aggregate mode is also called "gang mode" in other parts of this document. note: the unicast output gang mode (see section 9.3.25 unicast_aggregate_output_mode on page 106) must be set to a value greater than or equal to the multicast output gang mode. not used (3) write with a 0 to maintain future software compatibility. multicast_agg_in (2:0) selects aggregate of n. that is, n consecutive inputs are treated as a single input by the switch for multicast traffic. (2:0) = 3 - 7 are invalid. (2:0) = 2, n = 4. (2:0) = 1, n = 2. (2:0) = 0, n = 1. aggregate mode is also called "gang mode" in other parts of this document. field (bits) description
pmc-sierra, inc. pm73488 qse long form data sheet pmc-980616 issue 3 5 gbit/s atm switch fabric element released datasheet 107 format: refer to the following table. 9.3.26 switch_fabric_row address: 84 h type: read/write field (bits) description unicast_agg_out (2:0) selects aggregate of n. n consecutive outputs are treated as a single output by the switch for unicast traffic. (2:0) = 6 - 7 are invalid. (2:0) = 5 puts in the qse in randomization mode. (2:0) = 4, n = 16. (2:0) = 3, n = 8. (2:0) = 2, n = 4. (2:0) = 1, n = 2. (2:0) = 0, n = 1. note that this register determines whether the qse is in randomization mode or switching mode: when bits (2:0) have the value 5 then the qse is in randomization mode, and when bits (2:0) have a value between 4 and 0 then the qse is in switching mode. thus, for example, in a 3-stage switch fabric, all the qses in the 1st stage should have unicast_agg_out set to 5, and all the qses in the 2nd and 3rd stage should have unicast_agg_out set to values between 4 and 0. the rationale behind this encoding is that randomization mode may be viewed as switching mode with n = 32, because in randomization mode a unicast cell is "switched" to any of the 32 output ports. note that "aggregate mode" is also called "gang mode" in other parts of this document. note: the multicast output gang mode (see section 9.3.24 multicast_aggregate_output_and_input_modes on page 105) must be set to a value less than or equal to the unicast output gang mode
pmc-sierra, inc. pm73488 qse long form data sheet pmc-980616 issue 3 5 gbit/s atm switch fabric element released datasheet 108 format: refer to the following table. 9.3.27 switch_fabric_column address: 85 h type: read/write format: refer to the following table. field (bits) description (7:0) r pg where: r= the row number in the switching fabric for this switch element. the numbering of rows starts from 0. pg = the physical gang of the qse, which is defined as the number of output ports that physically connect this qse to a chip (qse or qrt) in the next stage. note that pg can have a value of 1,2,4,8, or 16 if the next stage consists of qses, and it can have a value of 1,2, or 4 if the next stage consists of qrts. if the value (r x pg ) exceeds 8 bit, the upper bits (i.e. msbs) should be truncated, to leave the lower 8 bits in the switch_fabric_row register. field (bits) description (7:0) c + 16p where: c = the column number in the switching fabric for this switch element. the numbering of columns starts from 0. p = the plane number if there are multiple parallel switch planes. the numbering of planes also starts from 0.
pmc-sierra, inc. pm73488 qse long form data sheet pmc-980616 issue 3 5 gbit/s atm switch fabric element released datasheet 109 9.3.28 cell_start_offset address: 86 h type: read/write format: refer to the following table. 9.3.29 bp_control_register address: 87 h type: read/write format: refer to the following table. note: the bp_control_register is typically used for fine-tuning multicast performance. for ini- tial system bring-up, this register may be left at the power-up default value. 9.3.30 ack_payload address: 88 h type: read/write format: refer to the following table. field (bits) description not used (7) write with a 0 to maintain future software compatibility. (6:0) offset between (external) cell_start and local cell_start (note: the cstart offset must only be changed when the device is in software reset. ) legal values for this register are between 0 and 117. field (bits) description not used (7:4) write with a 0 to maintain future software compatibility. global_limit_2 (3) if 1, second port threshold is off. global_limit_1 (2) if 1, first port threshold is off. per_port_limit (1) 1 each port allowed to have a maximum of 4 cells pending. 0 each port allowed to have a maximum of 3 cells pending. early_bp (0) 1 early (hence conservative) backpressure. 0 optimal backpressure. field (bits) description parity_nack (7:4) ack payload for parity error cells. reset to 8 h (default is onack).
pmc-sierra, inc. pm73488 qse long form data sheet pmc-980616 issue 3 5 gbit/s atm switch fabric element released datasheet 110 9.3.31 gang_dead_ack_payload address: 89 h type: read/write format: refer to the following table. 9.3.32 extended_switch_mode address: 8a h type: read format: refer to the following table. congestion_nack (3:0) ack payload for cells dropped due to congestion. reset to 4 h (default is mnack). field (bits) description not used (7:4) write with a 0 to maintain future software compatibility. gang_dead_nack (3:0) ack payload for cells dropped when an entire gang is disabled. a gang is defined as a set of consecutive outputs that is treated as a single output by the switch for unicast traffic (see unicast_aggregate_output_mode on page 106 ). this field resets to c h (which is interpreted by the qrt as an ack). field (bits) description latched_cell_start_out_ of_lock (0) cleared on read. set anytime cstart goes out of lock. field (bits) description
pmc-sierra, inc. pm73488 qse long form data sheet pmc-980616 issue 3 5 gbit/s atm switch fabric element released datasheet 111 10 jtag 10.1 jtag support the qrt supports the ieee boundary scan specification as described in the ieee 1149.1 standards. the test access port (tap) consists of the five standard pins, trstb, tck, tms, tdi and tdo, used to control the tap controller and the boundary scan registers. the trstb input is the active low reset signal used to reset the tap con- troller. tck is the test clock used to sample data on input, tdi and to output data on output, tdo. the tms input is used to direct the tap controller through its states. the basic boundary scan architecture is shown below. figure 42. boundary scan architecture the boundary scan architecture consists of a tap controller, an instruction register with instruction decode, a bypass register, a device identification register and a boundary scan register. the tap controller interprets the tms input and generates control signals to load the instruction and data registers. the instruction register with instruction decode block is used to select the test to be executed and/or the register to be accessed. the bypass register offers a single bit delay from primary input, tdi to primary output, tdo. the device identification register contains the device identification code. boundary scan register control tdi tdo device identification register bypass register instruction register and decode trstb tms tck test access port controller mux dff select tri-state enable
pmc-sierra, inc. pm73488 qse long form data sheet pmc-980616 issue 3 5 gbit/s atm switch fabric element released datasheet 112 the boundary scan register allows testing of board inter-connectivity. the boundary scan register consists of a shift register place in series with device inputs and outputs. using the boundary scan register, all digital inputs can be sampled and shifted out on primary output, tdo. in addition, patterns can be shifted in on primary input, tdi and forced onto all digital outputs. 10.2 tap controller the tap controller is a synchronous finite state machine clocked by the rising edge of primary input, tck. all state transitions are controlled using primary input, tms. the finite state machine is described below.
pmc-sierra, inc. pm73488 qse long form data sheet pmc-980616 issue 3 5 gbit/s atm switch fabric element released datasheet 113 figure 43. tap controller finite state machine 10.2.1 test-logic-reset: the test logic reset state is used to disable the tap logic when the device is in normal mode operation. the state is entered asynchronously by asserting input, trstb. the state is entered synchronously regardless of the current tap controller state by forcing input, tms high for 5 tck clock cycles. while in this state, the test-logic-reset run-test-idle select-dr-scan select-ir-scan capture-dr capture-ir shift-dr shift-ir exit1-dr exit1-ir pause-dr pause-ir exit2-dr exit2-ir update-dr update-ir trstb=0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 0 0 0 0 0 1 1 1 1 1 1 all transitions dependent on input tms 0 0 0 0 0 1
pmc-sierra, inc. pm73488 qse long form data sheet pmc-980616 issue 3 5 gbit/s atm switch fabric element released datasheet 114 instruction register is set to the idcode instruction. 10.2.2 run-test-idle: the run test/idle state is used to execute tests. 10.2.3 capture-dr: the capture data register state is used to load parallel data into the test data registers selected by the current instruction. if the selected register does not allow parallel loads or no loading is required by the current instruction, the test register maintains its value. loading occurs on the rising edge of tck. 10.2.4 shift-dr: the shift data register state is used to shift the selected test data registers by one stage. shifting is from msb to lsb and occurs on the rising edge of tck. 10.2.5 update-dr: the update data register state is used to load a test register's parallel output latch. in general, the output latches are used to control the device. for example, for the extest instruction, the boundary scan test reg- ister's parallel output latches are used to control the device's outputs. the parallel output latches are updated on the falling edge of tck. 10.2.6 capture-ir: the capture instruction register state is used to load the instruction register with a fixed instruction. the load occurs on the rising edge of tck. 10.2.7 shift-ir: the shift instruction register state is used to shift both the instruction register and the selected test data regis- ters by one stage. shifting is from msb to lsb and occurs on the rising edge of tck. 10.2.8 update-ir: the update instruction register state is used to load a new instruction into the instruction register. the new instruction must be scanned in using the shift-ir state. the load occurs on the falling edge of tck. the pause-dr and pause-ir states are provided to allow shifting through the test data and/or instruction reg- isters to be momentarily paused. the tdo output is enabled during states shift-dr and shift-ir. otherwise, it is tri-stated. 10.3 boundary scan instructions the following is a description of the standard instructions. each instruction selects an serial test data register path between input, tdi, and output, tdo. 10.3.1 bypass the bypass instruction shifts data from input tdi to output tdo with one tck clock period delay. the instruction is used to bypass the device. 10.3.2 extest the external test instruction allows testing of the interconnection to other devices. when the current instruc- tion is the extest instruction, the boundary scan register is place between input tdi and output tdo. pri- mary device inputs can be sampled by loading the boundary scan register using the capture-dr state. the sampled values can then be viewed by shifting the boundary scan register using the shift-dr state. primary device outputs can be controlled by loading patterns shifted in through input tdi into the boundary scan reg- ister using the update-dr state.
pmc-sierra, inc. pm73488 qse long form data sheet pmc-980616 issue 3 5 gbit/s atm switch fabric element released datasheet 115 10.3.3 sample the sample instruction samples all the device inputs and outputs. for this instruction, the boundary scan register is placed between tdi and tdo. primary device inputs and outputs can be sampled by loading the boundary scan register using the capture-dr state. the sampled values can then be viewed by shifting the boundary scan register using the shift-dr state. 10.3.4 idcode the identification instruction is used to connect the identification register between tdi and tdo. the device's identification code can then be shifted out using the shift-dr state. 10.3.5 stctest the single transport chain instruction is used to test out the tap controller and the boundary scan register during production test. when this instruction is the current instruction, the boundary scan register is con- nected between tdi and tdo. during the capture-dr state, the device identification code is loaded into the boundary scan register. the code can then be shifted out on output tdo using the shift-dr state. 10.4 boundary scan pin order table 32. boundary scan pin order order # pin # pin name pin type 0 hiz output enable 1 hiz output enable 2 hiz output enable 3 hiz output enable 4 hiz output enable 5 hiz output enable 6 hiz output enable 7 hiz output enable 8 hiz output enable 9 hiz output enable 10 g6 scan_enn clock 11 d3 oen clock 12 j6 cell_start clock 13 c2 cell_24_start clock 14 k6 stat_out_ndi output3 15 k6 stat_out_ndi input 16 e2 ctrl_in_ndo clock
pmc-sierra, inc. pm73488 qse long form data sheet pmc-980616 issue 3 5 gbit/s atm switch fabric element released datasheet 116 17 f3 se_d_in16.0 clock 18 c1 se_d_in16.1 clock 19 d2 se_d_in16.2 clock 20 h3 se_d_in16.3 clock 21 j5 se_soc_in16 clock 22 k5 se_d_in17.0 clock 23 k4 se_d_in17.1 clock 24 j4 se_d_in17.2 clock 25 g2 se_d_in17.3 clock 26 d1 se_soc_in17 clock 27 l5 se_d_in18.0 clock 28 j3 se_d_in18.1 clock 29 m6 se_d_in18.2 clock 30 n6 se_d_in18.3 clock 31 f1 se_soc_in18 clock 32 k3 se_d_in19.0 clock 33 h2 se_d_in19.1 clock 34 m5 se_d_in19.2 clock 35 l4 se_d_in19.3 clock 36 h1 se_soc_in19 clock 37 m3 se_d_in20.0 clock 38 j2 se_d_in20.1 clock 39 n4 se_d_in20.2 clock 40 g1 se_d_in20.3 clock 41 k1 se_soc_in20 clock 42 l2 se_d_in21.0 clock 43 n3 se_d_in21.1 clock 44 p6 se_d_in21.2 clock 45 n5 se_d_in21.3 clock
pmc-sierra, inc. pm73488 qse long form data sheet pmc-980616 issue 3 5 gbit/s atm switch fabric element released datasheet 117 46 r6 se_soc_in21 clock 47 m2 se_d_in22.0 clock 48 l1 se_d_in22.1 clock 49 p5 se_d_in22.2 clock 50 n2 se_d_in22.3 clock 51 r5 se_soc_in22 clock 52 p4 se_d_in23.0 clock 53 r4 se_d_in23.1 clock 54 p3 se_d_in23.2 clock 55 p1 se_d_in23.3 clock 56 m1 se_soc_in23 clock 57 r2 se_d_in24.0 clock 58 t2 se_d_in24.1 clock 59 r1 se_d_in24.2 clock 60 u1 se_d_in24.3 clock 61 t1 se_soc_in24 clock 62 t4 se_d_in25.0 clock 63 w1 se_d_in25.1 clock 64 t5 se_d_in25.2 clock 65 v2 se_d_in25.3 clock 66 u3 se_soc_in25 clock 67 y1 se_d_in26.0 clock 68 u4 se_d_in26.1 clock 69 t6 se_d_in26.2 clock 70 u5 se_d_in26.3 clock 71 u6 se_soc_in26 clock 72 v3 se_d_in27.0 clock 73 w2 se_d_in27.1 clock 74 aa1 se_d_in27.2 clock
pmc-sierra, inc. pm73488 qse long form data sheet pmc-980616 issue 3 5 gbit/s atm switch fabric element released datasheet 118 75 v5 se_d_in27.3 clock 76 v4 se_soc_in27 clock 77 y2 se_d_in28.0 clock 78 w3 se_d_in28.1 clock 79 ac1 se_d_in28.2 clock 80 ad1 se_d_in28.3 clock 81 w5 se_soc_in28 clock 82 ab2 se_d_in29.0 clock 83 aa3 se_d_in29.1 clock 84 y4 se_d_in29.2 clock 85 v6 se_d_in29.3 clock 86 w6 se_soc_in29 clock 87 ac2 se_d_in30.0 clock 88 y5 se_d_in30.1 clock 89 ae1 se_d_in30.2 clock 90 ad2 se_d_in30.3 clock 91 ab3 se_soc_in30 clock 92 aa4 se_d_in31.0 clock 93 aa5 se_d_in31.1 clock 94 ag1 se_d_in31.2 clock 95 ac3 se_d_in31.3 clock 96 ab4 se_soc_in31 clock 97 ah1 ram_add.17 output3 98 ab5 bp_ack_out.0 output3 99 af2 bp_ack_out.1 output3 100 aa6 bp_ack_out.2 output3 101 ag2 bp_ack_out.3 output3 102 ab6 bp_ack_out.4 output3 103 ae3 bp_ack_out.5 output3
pmc-sierra, inc. pm73488 qse long form data sheet pmc-980616 issue 3 5 gbit/s atm switch fabric element released datasheet 119 104 ac5 bp_ack_out.6 output3 105 ah2 bp_ack_out.7 output3 106 ad4 bp_ack_out.8 output3 107 ad6 bp_ack_out.9 output3 108 ag3 bp_ack_out.10 output3 109 ae4 bp_ack_out.11 output3 110 ad5 bp_ack_out.12 output3 111 ae5 bp_ack_out.13 output3 112 af4 bp_ack_out.14 output3 113 aj1 bp_ack_out.15 output3 114 ak2 bp_ack_out.16 output3 115 ag5 bp_ack_out.17 output3 116 af6 bp_ack_out.18 output3 117 af7 bp_ack_out.19 output3 118 ag6 bp_ack_out.20 output3 119 ah4 bp_ack_out.21 output3 120 ae7 bp_ack_out.22 output3 121 ag7 bp_ack_out.23 output3 122 aj3 bp_ack_out.24 output3 123 af8 bp_ack_out.25 output3 124 ah6 bp_ack_out.26 output3 125 ae9 bp_ack_out.27 output3 126 aj4 bp_ack_out.28 output3 127 ae10 bp_ack_out.29 output3 128 aj5 bp_ack_out.30 output3 129 af9 bp_ack_out.31 output3 130 ak3 add.0 clock 131 ag9 add.1 clock 132 ah8 add.2 clock
pmc-sierra, inc. pm73488 qse long form data sheet pmc-980616 issue 3 5 gbit/s atm switch fabric element released datasheet 120 133 ak4 add.3 clock 134 af10 add.4 clock 135 ag10 add.5 clock 136 ah9 add.6 clock 137 aj7 add.7 clock 138 ak6 data.0 output3 139 ak6 data.0 input 140 af11 data.1 output3 141 af11 data.1 input 142 aj8 data.2 output3 143 aj8 data.2 input 144 ae12 data.3 output3 145 ae12 data.3 input 146 ae13 data.4 output3 147 ae13 data.4 input 148 ag11 data.5 output3 149 ag11 data.5 input 150 ah10 data.6 output3 151 ah10 data.6 input 152 aj9 data.7 output3 153 aj9 data.7 input 154 af12 ram_add.18 output3 155 ak7 csn clock 156 ak8 rdn clock 157 ah12 wrn clock 158 aj11 ackn output3 159 ag13 intrn output3 160 af13 reset clock 161 ak10 se_d_out31.0 output3
pmc-sierra, inc. pm73488 qse long form data sheet pmc-980616 issue 3 5 gbit/s atm switch fabric element released datasheet 121 162 aj12 se_d_out31.1 output3 163 ah13 se_d_out31.2 output3 164 ae14 se_d_out31.3 output3 165 af14 se_d_out30.0 output3 166 ae15 se_d_out30.1 output3 167 ag14 se_d_out30.2 output3 168 ak11 se_d_out30.3 output3 169 ah14 se_d_out29.0 output3 170 aj13 se_d_out29.1 output3 171 af15 se_d_out29.2 output3 172 ak12 se_d_out29.3 output3 173 ag15 se_d_out28.0 output3 174 ak15 se_d_out28.1 output3 175 ak14 se_d_out28.2 output3 176 ak16 se_d_out28.3 output3 177 aj15 se_soc_out7 output3 178 ak19 se_d_out27.0 output3 179 ak17 se_d_out27.1 output3 180 ah17 se_d_out27.2 output3 181 ag16 se_d_out27.3 output3 182 ag17 se_d_out26.0 output3 183 af16 se_d_out26.1 output3 184 aj18 se_d_out26.2 output3 185 af17 se_d_out26.3 output3 186 ak20 se_d_out25.0 output3 187 aj19 se_d_out25.1 output3 188 ae16 se_d_out25.2 output3 189 af18 se_d_out25.3 output3 190 ae17 se_d_out24.0 output3
pmc-sierra, inc. pm73488 qse long form data sheet pmc-980616 issue 3 5 gbit/s atm switch fabric element released datasheet 122 191 ah18 se_d_out24.1 output3 192 aj20 se_d_out24.2 output3 193 ak21 se_d_out24.3 output3 194 ak24 se_soc_out6 output3 195 ag18 se_d_out23.0 output3 196 aj22 se_d_out23.1 output3 197 ah19 se_d_out23.2 output3 198 ak23 se_d_out23.3 output3 199 ag20 se_d_out22.0 output3 200 af19 se_d_out22.1 output3 201 aj23 se_d_out22.2 output3 202 ah21 se_d_out22.3 output3 203 ak25 se_d_out21.0 output3 204 ae18 se_d_out21.1 output3 205 ae19 se_d_out21.2 output3 206 ah22 se_d_out21.3 output3 207 af20 se_d_out20.0 output3 208 ak27 se_d_out20.1 output3 209 aj24 se_d_out20.2 output3 210 ag22 se_d_out20.3 output3 211 ag21 se_soc_out5 output3 212 af21 se_d_out19.0 output3 213 af22 se_d_out19.1 output3 214 ah23 se_d_out19.2 output3 215 aj27 se_d_out19.3 output3 216 ak28 se_d_out18.0 output3 217 ah25 se_d_out18.1 output3 218 aj26 se_d_out18.2 output3 219 ae21 se_d_out18.3 output3
pmc-sierra, inc. pm73488 qse long form data sheet pmc-980616 issue 3 5 gbit/s atm switch fabric element released datasheet 123 220 aj28 se_d_out17.0 output3 221 ae22 se_d_out17.1 output3 222 ah27 se_d_out17.2 output3 223 af23 se_d_out17.3 output3 224 af24 se_d_out16.0 output3 225 ag24 se_d_out16.1 output3 226 ae24 se_d_out16.2 output3 227 ag26 se_d_out16.3 output3 228 ag25 se_soc_out4 output3 229 af25 se_clk_bypass clock 230 ak29 se_d_out15.0 output3 231 ae26 se_d_out15.1 output3 232 ad26 se_d_out15.2 output3 233 ae27 se_d_out15.3 output3 234 ag28 se_d_out14.0 output3 235 ad25 se_d_out14.1 output3 236 ad27 se_d_out14.2 output3 237 ah29 se_d_out14.3 output3 238 ac26 se_d_out13.0 output3 239 ae28 se_d_out13.1 output3 240 ab25 se_d_out13.2 output3 241 ag29 se_d_out13.3 output3 242 aa25 se_d_out12.0 output3 243 af29 se_d_out12.1 output3 244 ab26 se_d_out12.2 output3 245 ah30 se_d_out12.3 output3 246 ab27 se_soc_out3 output3 247 ac28 se_d_out11.0 output3 248 ag30 se_d_out11.1 output3
pmc-sierra, inc. pm73488 qse long form data sheet pmc-980616 issue 3 5 gbit/s atm switch fabric element released datasheet 124 249 aa26 se_d_out11.2 output3 250 aa27 se_d_out11.3 output3 251 ab28 se_d_out10.0 output3 252 ad29 se_d_out10.1 output3 253 ae30 se_d_out10.2 output3 254 y26 se_d_out10.3 output3 255 ac29 se_d_out09.0 output3 256 w25 se_d_out09.1 output3 257 v25 se_d_out09.2 output3 258 y27 se_d_out09.3 output3 259 aa28 se_d_out08.0 output3 260 ab29 se_d_out08.1 output3 261 w26 se_d_out08.2 output3 262 ad30 se_d_out08.3 output3 263 ac30 se_soc_out2 output3 264 w28 se_d_out07.0 output3 265 y29 se_d_out07.1 output3 266 v27 se_d_out07.2 output3 267 v26 se_d_out07.3 output3 268 aa30 se_d_out06.0 output3 269 w29 se_d_out06.1 output3 270 v28 se_d_out06.2 output3 271 u25 se_d_out06.3 output3 272 u26 se_d_out05.0 output3 273 t25 se_d_out05.1 output3 274 u27 se_d_out05.2 output3 275 y30 se_d_out05.3 output3 276 u28 se_d_out04.0 output3 277 v29 se_d_out04.1 output3
pmc-sierra, inc. pm73488 qse long form data sheet pmc-980616 issue 3 5 gbit/s atm switch fabric element released datasheet 125 278 t26 se_d_out04.2 output3 279 w30 se_d_out04.3 output3 280 t27 se_soc_out1 output3 281 t30 se_d_out03.0 output3 282 u30 se_d_out03.1 output3 283 r30 se_d_out03.2 output3 284 t29 se_d_out03.3 output3 285 r29 se_d_out02.0 output3 286 m30 se_d_out02.1 output3 287 p30 se_d_out02.2 output3 288 p28 se_d_out02.3 output3 289 r27 se_d_out01.0 output3 290 p27 se_d_out01.1 output3 291 r26 se_d_out01.2 output3 292 n29 se_d_out01.3 output3 293 p26 se_d_out00.0 output3 294 l30 se_d_out00.1 output3 295 m29 se_d_out00.2 output3 296 r25 se_d_out00.3 output3 297 n26 se_soc_out0 output3 298 p25 pll_bypass_n clock 299 l29 bp_ack_in.0 clock 300 k30 bp_ack_in.1 clock 301 g30 bp_ack_in.2 clock 302 n27 bp_ack_in.3 clock 303 j29 bp_ack_in.4 clock 304 m28 bp_ack_in.5 clock 305 h30 bp_ack_in.6 clock 306 l27 bp_ack_in.7 clock
pmc-sierra, inc. pm73488 qse long form data sheet pmc-980616 issue 3 5 gbit/s atm switch fabric element released datasheet 126 307 m26 bp_ack_in.8 clock 308 h29 bp_ack_in.9 clock 309 k28 bp_ack_in.10 clock 310 f30 bp_ack_in.11 clock 311 n25 bp_ack_in.12 clock 312 m25 bp_ack_in.13 clock 313 j28 bp_ack_in.14 clock 314 l26 bp_ack_in.15 clock 315 d30 bp_ack_in.16 clock 316 g29 bp_ack_in.17 clock 317 j27 bp_ack_in.18 clock 318 k27 bp_ack_in.19 clock 319 k26 bp_ack_in.20 clock 320 j26 bp_ack_in.21 clock 321 h28 bp_ack_in.22 clock 322 d29 bp_ack_in.23 clock 323 c30 bp_ack_in.24 clock 324 f28 bp_ack_in.25 clock 325 e29 bp_ack_in.26 clock 326 k25 bp_ack_in.27 clock 327 c29 bp_ack_in.28 clock 328 j25 bp_ack_in.29 clock 329 d28 bp_ack_in.30 clock 330 h26 bp_ack_in.31 clock 331 g26 ram_add.0 output3 332 g27 ram_add.1 output3 333 g25 ram_add.2 output3 334 e27 ram_add.3 output3 335 f27 ram_add.4 output3
pmc-sierra, inc. pm73488 qse long form data sheet pmc-980616 issue 3 5 gbit/s atm switch fabric element released datasheet 127 336 f26 ram_add.5 output3 337 b30 ram_add.6 output3 338 a29 ram_add.7 output3 339 e25 ram_add.8 output3 340 d25 ram_add.9 output3 341 d26 ram_add.10 output3 342 f24 ram_add.11 output3 343 d24 ram_add.12 output3 344 e24 ram_add.13 output3 345 e23 ram_add.14 output3 346 c27 ram_add.15 output3 347 f22 ram_data.0 output3 348 f22 ram_data.0 input 349 b28 ram_data.1 output3 350 b28 ram_data.1 input 351 f21 ram_data.2 output3 352 f21 ram_data.2 input 353 b26 ram_data.3 output3 354 b26 ram_data.3 input 355 c25 ram_data.4 output3 356 c25 ram_data.4 input 357 a28 ram_data.5 output3 358 a28 ram_data.5 input 359 b27 ram_data.6 output3 360 b27 ram_data.6 input 361 c23 ram_data.7 output3 362 c23 ram_data.7 input 363 e22 ram_data.8 output3 364 e22 ram_data.8 input
pmc-sierra, inc. pm73488 qse long form data sheet pmc-980616 issue 3 5 gbit/s atm switch fabric element released datasheet 128 365 e21 ram_data.9 output3 366 e21 ram_data.9 input 367 d21 ram_data.10 output3 368 d21 ram_data.10 input 369 d22 ram_data.11 output3 370 d22 ram_data.11 input 371 b24 ram_data.12 output3 372 b24 ram_data.12 input 373 a27 ram_data.13 output3 374 a27 ram_data.13 input 375 e20 ram_data.14 output3 376 e20 ram_data.14 input 377 c22 ram_data.15 output3 378 c22 ram_data.15 input 379 f19 ram_add.16 output3 380 f18 ram_parity output3 381 f18 ram_parity input 382 a25 ram_wrn output3 383 c21 ram_oen output3 384 b23 ram_clk output3 385 e19 se_d_in00.0 clock 386 d20 se_d_in00.1 clock 387 a23 se_d_in00.2 clock 388 c19 se_d_in00.3 clock 389 b22 se_soc_in00 clock 390 d18 se_d_in01.0 clock 391 a24 se_d_in01.1 clock 392 a21 se_d_in01.2 clock 393 b20 se_d_in01.3 clock
pmc-sierra, inc. pm73488 qse long form data sheet pmc-980616 issue 3 5 gbit/s atm switch fabric element released datasheet 129 394 c18 se_soc_in01 clock 395 f17 se_d_in02.0 clock 396 e18 se_d_in02.1 clock 397 f16 se_d_in02.2 clock 398 b19 se_d_in02.3 clock 399 a20 se_soc_in02 clock 400 e17 se_d_in03.0 clock 401 b18 se_d_in03.1 clock 402 e16 se_d_in03.2 clock 403 d17 se_d_in03.3 clock 404 d16 se_soc_in03 clock 405 c17 se_d_in04.0 clock 406 a17 se_d_in04.1 clock 407 a19 se_d_in04.2 clock 408 b16 se_d_in04.3 clock 409 b15 se_soc_in04 clock 410 a16 se_d_in05.0 clock 411 a14 se_d_in05.1 clock 412 a15 se_d_in05.2 clock 413 d15 se_d_in05.3 clock 414 a12 se_soc_in05 clock 415 e15 se_d_in06.0 clock 416 b13 se_d_in06.1 clock 417 c14 se_d_in06.2 clock 418 a11 se_d_in06.3 clock 419 d14 se_soc_in06 clock 420 f15 se_d_in07.0 clock 421 e14 se_d_in07.1 clock 422 f14 se_d_in07.2 clock
pmc-sierra, inc. pm73488 qse long form data sheet pmc-980616 issue 3 5 gbit/s atm switch fabric element released datasheet 130 423 c13 se_d_in07.3 clock 424 b12 se_soc_in07 clock 425 a10 se_d_in08.0 clock 426 e13 se_d_in08.1 clock 427 d13 se_d_in08.2 clock 428 b11 se_d_in08.3 clock 429 c12 se_soc_in08 clock 430 a8 se_d_in09.0 clock 431 a7 se_d_in09.1 clock 432 e12 se_d_in09.2 clock 433 b9 se_d_in09.3 clock 434 c10 se_soc_in09 clock 435 d11 se_d_in10.0 clock 436 f13 se_d_in10.1 clock 437 f12 se_d_in10.2 clock 438 b8 se_d_in10.3 clock 439 e11 se_soc_in10 clock 440 a6 se_d_in11.0 clock 441 b7 se_d_in11.1 clock 442 c9 se_d_in11.2 clock 443 d10 se_d_in11.3 clock 444 e10 se_soc_in11 clock 445 a4 se_d_in12.0 clock 446 c8 se_d_in12.1 clock 447 d9 se_d_in12.2 clock 448 a3 se_d_in12.3 clock 449 e9 se_soc_in12 clock 450 b5 se_d_in13.0 clock 451 f10 se_d_in13.1 clock
pmc-sierra, inc. pm73488 qse long form data sheet pmc-980616 issue 3 5 gbit/s atm switch fabric element released datasheet 131 452 b4 se_d_in13.2 clock 453 f9 se_d_in13.3 clock 454 c6 se_soc_in13 clock 455 e8 se_d_in14.0 clock 456 b3 se_d_in14.1 clock 457 d7 se_d_in14.2 clock 458 f7 se_d_in14.3 clock 459 c4 se_soc_in14 clock 460 d6 se_d_in15.0 clock 461 e7 se_d_in15.1 clock 462 e6 se_d_in15.2 clock 463 d5 se_d_in15.3 clock 464 a2 se_soc_in15 clock
pmc-sierra, inc. pm73488 qse long form data sheet pmc-980616 issue 3 5 gbit/s atm switch fabric element released datasheet 132 appendix a nomenclature a.1 definitions transmit signals: all signals related to processing the data heading towards the optical/electrical layer. receive signals: all signals related to processing the data heading towards the atm layer. a.2 numbers ? hexadecimal numbers are followed by the suffix h , for example: 1 h , 2c h . ? binary numbers are followed by the suffix b , for example: 00 b . ? decimal numbers appear without suffixes. a.3 glossary of abbreviations table 33. standard abbreviations abbreviation description ack acknowledgment atm asynchronous transfer mode clp cell loss priority cmos complementary metal oxide semiconductor cpu central processing unit epbga enhanced plastic ball grid array irt input half of qrt jtag joint test access group mb mark bit mc multicast mgi multicast group index mgv multicast group vector mnack mid switch negative acknowledgment mpv multicast port vector nack negative acknowledgment onack output negative acknowledgment ort output half of qrt pg physical gang phy physical
pmc-sierra, inc. pm73488 qse long form data sheet pmc-980616 issue 3 5 gbit/s atm switch fabric element released datasheet 133 pif general-purpose microprocessor interface pll phase locked loop pti payload type indicator qrt pmcs atm traffic management chip (pm73487) qse pmcs atm switch fabric chip (pm73488) ram random access memory sf speedup factor soc start-of-cell sp spare bit sram static random access memory ssram synchronous static random access memory utopia universal test and operations phy interface for atm vc virtual channel vci virtual channel identifier table 33. standard abbreviations (continued) abbreviation description
pmc-sierra, inc. pm73488 qse long form data sheet pmc-980616 issue 3 5 gbit/s atm switch fabric element released datasheet 134 appendix b references ?atm forum, atm user-network interface specification , v3.0, september 10, 1993. ? ieee 1149.1, standard test access port and boundary scan architecture , may 21, 1990. ? itu (ccitt) recommendation i.432, b-isdn user-network interface - physical interface specification , june 1990. ?utopia, an atm phy data path interface, level 1 , v2.01, february, 1994.
pmc-sierra, inc. pm73488 qse long form data sheet pmc-980616 issue 3 5 gbit/s atm switch fabric element released datasheet 135 ordering information table 34 lists the ordering information. table 34. ordering information part number description PM73488-PI 596-pin enhanced plastic ball grid array (epbga) package
pmc-sierra, inc. pm73488 qse long form data sheet pmc-980616 issue 3 5 gbit/s atm switch fabric element released datasheet 136 notes
pmc-sierra, inc. pm73488 qse long form data sheet pmc-980616 issue 3 5 gbit/s atm switch fabric element released datasheet 137 none of the information contained in this document constitutes an express or implied warranty by pmc-sierra, inc. as to the suf ficiency, fitness, or suitability for a particular purpose of any such information of the fitness or suitability for a particular purpose, merchantab ility, performance, compatibility with other parts or systems, of any of the products of pmc-sierra, inc., or any portion thereof, referred to in this document. pmc-sierra, inc. expressly disclaims all representations and warranties of any kind regarding the contents or use of the information, including, but not l imited to, express and implied warranties of accuracy, completeness, merchantability, fitness for a particular use, or non-infringement. in no event will pmc-sierra, inc. be liable for any direct, indirect, special, incidental or consequential damages, including, but not limited to, lost profits, lost business or lost data resulting from any use or reliance upon the information, whether or not pmc-sierra, inc. has been ad vised of the possibility of such damage. ? 1999 pmc-sierra, inc. pmc-980616 (r3) ref pmc-981002 (r2) issue date: june 1999 contacting pmc-sierra, inc. pmc-sierra, inc. 105-8555 baxter place burnaby b.c. canada v5a 4v7 tel: (604) 415-6000 fax: (604) 415-6200 document information: document@pmc-sierra.com corporate information: info@pmc-sierra.com application information: apps@pmc-sierra.com (604) 415-4533 web site: http://www.pmc-sierra.com

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